Cell (processor)
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POWER, PowerPC, and Power ISA architectures |
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Cancelled in gray, historic in italic |
Cell is a 64-bit
It was developed by Sony, Toshiba, and IBM, an alliance known as "STI". The architectural design and first implementation were carried out at the STI Design Center in Austin, Texas over a four-year period beginning March 2001 on a budget reported by Sony as approaching US$400 million.[3] Cell is shorthand for Cell Broadband Engine Architecture, commonly abbreviated CBEA in full or Cell BE in part.
The first major commercial application of Cell was in Sony's
The Cell architecture includes a
History
In mid-2000,
The STI Design Center opened in March 2001.
The design with 4 PPEs and 32 SPEs was never realized. Instead, Sony and IBM only manufactured a design with one PPE and 8 SPEs. This smaller design, the Cell Broadband Engine or Cell/BE was fabricated using a
In March 2007, IBM announced that the
In February 2008, IBM announced that it would begin to fabricate Cell processors with the
In May 2008, IBM introduced the high-performance double-precision floating-point version of the Cell processor, the
In May 2008, an
In August 2009 the 45 nm Cell processor was introduced in concert with Sony's
By November 2009, IBM had discontinued the development of a Cell processor with 32 APUs[15][16] but was still developing other Cell products.[17]
Commercialization
This article needs to be updated.(November 2010) |
On May 17, 2005, Sony Computer Entertainment confirmed some specifications of the Cell processor that would be shipping in the then-forthcoming
The relationship between
On June 28, 2005, IBM and
In the fall of 2006, IBM released the QS20
Sony's high-performance media computing server ZEGO uses a 3.2 GHz Cell/B.E processor.
Overview
The Cell Broadband Engine, or Cell as it is more commonly known, is a microprocessor intended as a hybrid of conventional desktop processors (such as the
In a simple analysis, the Cell processor can be split into four components: external input and output structures, the main processor called the Power Processing Element (PPE) (a two-way
To achieve the high performance needed for mathematically intensive tasks, such as decoding/encoding
The PPE, which is capable of running a conventional operating system, has control over the SPEs and can start, stop, interrupt, and schedule processes running on the SPEs. To this end, the PPE has additional instructions relating to the control of the SPEs. Unlike SPEs, the PPE can read and write the main memory and the local memories of SPEs through the standard load/store instructions. Despite having
The PPE and bus architecture includes various modes of operation giving different levels of memory protection, allowing areas of memory to be protected from access by specific processes running on the SPEs or the PPE.
Both the PPE and SPE are
PowerXCell 8i
In 2008, IBM announced a revised variant of the Cell called the PowerXCell 8i,
Since the PowerXCell 8i removed the RAMBUS memory interface, and added significantly larger DDR2 interfaces and enhanced SPEs, the chip layout had to be reworked, which resulted in both larger chip die and packaging.[30]
Architecture
While the Cell chip can have a number of different configurations, the basic configuration is a
Power Processor Element (PPE)
The PPE
Xenon in Xbox 360
The PPE was designed specifically for the Cell processor but during development, Microsoft approached IBM wanting a high-performance processor core for its Xbox 360. IBM complied and made the tri-core Xenon processor, based on a slightly modified version of the PPE with added VMX128 extensions.[37][38]
Synergistic Processing Elements (SPE)
Each SPE is a dual issue in order processor composed of a "Synergistic Processing Unit",
In one typical usage scenario, the system will load the SPEs with small programs (similar to
Compared to its personal computer contemporaries, the relatively high overall floating-point performance of a Cell processor seemingly dwarfs the abilities of the SIMD unit in CPUs like the Pentium 4 and the Athlon 64. However, comparing only floating-point abilities of a system is a one-dimensional and application-specific metric. Unlike a Cell processor, such desktop CPUs are more suited to the general-purpose software usually run on personal computers. In addition to executing multiple instructions per clock, processors from Intel and AMD feature branch predictors. The Cell is designed to compensate for this with compiler assistance, in which prepare-to-branch instructions are created. For double-precision floating-point operations, as sometimes used in personal computers and often used in scientific computing, Cell performance drops by an order of magnitude, but still reaches 20.8 GFLOPS (1.8 GFLOPS per SPE, 6.4 GFLOPS per PPE). The PowerXCell 8i variant, which was specifically designed for double-precision, reaches 102.4 GFLOPS in double-precision calculations.[42]
Tests by IBM show that the SPEs can reach 98% of their theoretical peak performance running optimized parallel matrix multiplication.[36]
Each SPE has a local memory of 256 KB.[43] In total, the SPEs have 2 MB of local memory.
Element Interconnect Bus (EIB)
The EIB is a communication bus internal to the Cell processor which connects the various on-chip system elements: the PPE processor, the memory controller (MIC), the eight SPE coprocessors, and two off-chip I/O interfaces, for a total of 12 participants in the PS3 (the number of SPU can vary in industrial applications). The EIB also includes an arbitration unit which functions as a set of traffic lights. In some documents, IBM refers to EIB participants as 'units'.
The EIB is presently implemented as a circular ring consisting of four 16-byte-wide unidirectional channels which counter-rotate in pairs. When traffic patterns permit, each channel can convey up to three transactions concurrently. As the EIB runs at half the system clock rate the effective channel rate is 16 bytes every two system clocks. At maximum concurrency, with three active transactions on each of the four rings, the peak instantaneous EIB bandwidth is 96 bytes per clock (12 concurrent transactions × 16 bytes wide / 2 system clocks per transfer). While this figure is often quoted in IBM literature, it is unrealistic to simply scale this number by processor clock speed. The arbitration unit imposes additional constraints.
IBM Senior Engineer David Krolak, EIB lead designer, explains the concurrency model:
A ring can start a new op every three cycles. Each transfer always takes eight beats. That was one of the simplifications we made, it's optimized for streaming a lot of data. If you do small ops, it does not work quite as well. If you think of eight-car trains running around this track, as long as the trains aren't running into each other, they can coexist on the track.[44]
Each participant on the EIB has one 16-byte read port and one 16-byte write port. The limit for a single participant is to read and write at a rate of 16 bytes per EIB clock (for simplicity often regarded 8 bytes per system clock). Each SPU processor contains a dedicated DMA management queue capable of scheduling long sequences of transactions to various endpoints without interfering with the SPU's ongoing computations; these DMA queues can be managed locally or remotely as well, providing additional flexibility in the control model.
Data flows on an EIB channel stepwise around the ring. Since there are twelve participants, the total number of steps around the channel back to the point of origin is twelve. Six steps is the longest distance between any pair of participants. An EIB channel is not permitted to convey data requiring more than six steps; such data must take the shorter route around the circle in the other direction. The number of steps involved in sending the packet has very little impact on transfer latency: the clock speed driving the steps is very fast relative to other considerations. However, longer communication distances are detrimental to the overall performance of the EIB as they reduce available concurrency.
Despite IBM's original desire to implement the EIB as a more powerful cross-bar, the circular configuration they adopted to spare resources rarely represents a limiting factor on the performance of the Cell chip as a whole. In the worst case, the programmer must take extra care to schedule communication patterns where the EIB is able to function at high concurrency levels.
David Krolak explained:
Well, in the beginning, early in the development process, several people were pushing for a crossbar switch, and the way the bus is designed, you could actually pull out the EIB and put in a crossbar switch if you were willing to devote more silicon space on the chip to wiring. We had to find a balance between connectivity and area, and there just was not enough room to put a full crossbar switch in. So we came up with this ring structure which we think is very interesting. It fits within the area constraints and still has very impressive bandwidth.[44]
Bandwidth assessment
At 3.2 GHz, each channel flows at a rate of 25.6 GB/s. Viewing the EIB in isolation from the system elements it connects, achieving twelve concurrent transactions at this flow rate works out to an abstract EIB bandwidth of 307.2 GB/s. Based on this view many IBM publications depict available EIB bandwidth as "greater than 300 GB/s". This number reflects the peak instantaneous EIB bandwidth scaled by processor frequency.[45]
However, other technical restrictions are involved in the arbitration mechanism for packets accepted onto the bus. The IBM Systems Performance group explained:
Each unit on the EIB can simultaneously send and receive 16 bytes of data every bus cycle. The maximum data bandwidth of the entire EIB is limited by the maximum rate at which addresses are snooped across all units in the system, which is one per bus cycle. Since each snooped address request can potentially transfer up to 128 bytes, the theoretical peak data bandwidth on the EIB at 3.2 GHz is 128Bx1.6 GHz = 204.8 GB/s.[36]
This quote apparently represents the full extent of IBM's public disclosure of this mechanism and its impact. The EIB arbitration unit, the snooping mechanism, and interrupt generation on segment or page translation faults are not well described in the documentation set as yet made public by IBM.[citation needed]
In practice, effective EIB bandwidth can also be limited by the ring participants involved. While each of the nine processing cores can sustain 25.6 GB/s read and write concurrently, the memory interface controller (MIC) is tied to a pair of XDR memory channels permitting a maximum flow of 25.6 GB/s for reads and writes combined and the two IO controllers are documented as supporting a peak combined input speed of 25.6 GB/s and a peak combined output speed of 35 GB/s.
To add further to the confusion, some older publications cite EIB bandwidth assuming a 4 GHz system clock. This reference frame results in an instantaneous EIB bandwidth figure of 384 GB/s and an arbitration-limited bandwidth figure of 256 GB/s.
All things considered the theoretic 204.8 GB/s number most often cited is the best one to bear in mind. The IBM Systems Performance group has demonstrated SPU-centric data flows achieving 197 GB/s on a Cell processor running at 3.2 GHz so this number is a fair reflection on practice as well.[36]
Memory and I/O controllers
Cell contains a dual channel Rambus XIO macro which interfaces to Rambus XDR memory. The memory interface controller (MIC) is separate from the XIO macro and is designed by IBM. The XIO-XDR link runs at 3.2 Gbit/s per pin. Two 32-bit channels can provide a theoretical maximum of 25.6 GB/s.
The I/O interface, also a Rambus design, is known as FlexIO. The FlexIO interface is organized into 12 lanes, each lane being a unidirectional 8-bit wide point-to-point path. Five 8-bit wide point-to-point paths are inbound lanes to Cell, while the remaining seven are outbound. This provides a theoretical peak bandwidth of 62.4 GB/s (36.4 GB/s outbound, 26 GB/s inbound) at 2.6 GHz. The FlexIO interface can be clocked independently, typ. at 3.2 GHz. 4 inbound + 4 outbound lanes are supporting memory coherency.
Possible applications
Video processing card
Some companies, such as
Blade server
On August 29, 2007, IBM announced the
On May 13, 2008, IBM announced the
IBM has discontinued the Blade server line based on Cell processors as of January 12, 2012.[49]
PCI Express board
Several companies provide PCI-e boards utilising the IBM PowerXCell 8i. The performance is reported as 179.2 GFlops (SP), 89.6 GFlops (DP) at 2.8 GHz.[50][51]
Console video games
Home cinema
Toshiba has produced HDTVs using Cell. They presented a system to decode 48 standard definition MPEG-2 streams simultaneously on a 1920×1080 screen.[52][53] This can enable a viewer to choose a channel based on dozens of thumbnail videos displayed simultaneously on the screen.
Supercomputing
IBM's supercomputer,
Cluster computing
Clusters of PlayStation 3 consoles are an attractive alternative to high-end systems based on Cell blades. Innovative Computing Laboratory, a group led by Jack Dongarra, in the Computer Science Department at the University of Tennessee, investigated such an application in depth.[56] Terrasoft Solutions is selling 8-node and 32-node PS3 clusters with Yellow Dog Linux pre-installed, an implementation of Dongarra's research.
As first reported by Wired on October 17, 2007,[57] an interesting application of using PlayStation 3 in a cluster configuration was implemented by Astrophysicist Gaurav Khanna, from the Physics department of University of Massachusetts Dartmouth, who replaced time used on supercomputers with a cluster of eight PlayStation 3s. Subsequently, the next generation of this machine, now called the PlayStation 3 Gravity Grid, uses a network of 16 machines, and exploits the Cell processor for the intended application which is binary black hole coalescence using perturbation theory. In particular, the cluster performs astrophysical simulations of large supermassive black holes capturing smaller compact objects and has generated numerical data that has been published multiple times in the relevant scientific research literature.[58] The Cell processor version used by the PlayStation 3 has a main CPU and 6 SPEs available to the user, giving the Gravity Grid machine a net of 16 general-purpose processors and 96 vector processors. The machine has a one-time cost of $9,000 to build and is adequate for black-hole simulations which would otherwise cost $6,000 per run on a conventional supercomputer. The black hole calculations are not memory-intensive and are highly localizable, and so are well-suited to this architecture. Khanna claims that the cluster's performance exceeds that of a 100+ Intel Xeon core based traditional Linux cluster on his simulations. The PS3 Gravity Grid gathered significant media attention through 2007,[59] 2008,[60][61] 2009,[62][63][64] and 2010.[65][66]
The computational Biochemistry and Biophysics lab at the
for collaborative computing based on the CellMD software, the first one designed specifically for the Cell processor.The United States
Distributed computing
With the help of the computing power of over half a million PlayStation 3 consoles, the distributed computing project
Mainframes
IBM announced on April 25, 2007, that it would begin integrating its Cell Broadband Engine Architecture microprocessors into the company's System z line of mainframes.[70] This has led to a gameframe.
Password cracking
The architecture of the processor makes it better suited to hardware-assisted cryptographic brute-force attack applications than conventional processors.[71]
Software engineering
Due to the flexible nature of the Cell, there are several possibilities for the utilization of its resources, not limited to just different computing paradigms:[72]
Job queue
The PPE maintains a job queue, schedules jobs in SPEs, and monitors progress. Each SPE runs a "mini kernel" whose role is to fetch a job, execute it, and synchronize with the PPE.
Self-multitasking of SPEs
The mini kernel and scheduling is distributed across the SPEs. Tasks are synchronized using mutexes or semaphores as in a conventional operating system. Ready-to-run tasks wait in a queue for an SPE to execute them. The SPEs use shared memory for all tasks in this configuration.
Stream processing
Each SPE runs a distinct program. Data comes from an input stream and is sent to SPEs. When an SPE has terminated the processing, the output data is sent to an output stream.
This provides a flexible and powerful architecture for stream processing, and allows explicit scheduling for each SPE separately. Other processors are also able to perform streaming tasks but are limited by the kernel loaded.
Open source software development
In 2005, patches enabling Cell support in the Linux kernel were submitted for inclusion by IBM developers.[73] Arnd Bergmann (one of the developers of the aforementioned patches) also described the Linux-based Cell architecture at LinuxTag 2005.[74] As of release 2.6.16 (March 20, 2006), the Linux kernel officially supports the Cell processor.[75]
Both PPE and SPEs are programmable in C/C++ using a common API provided by libraries.
Fixstars Solutions provides Yellow Dog Linux for IBM and Mercury Cell-based systems, as well as for the PlayStation 3.[76] Terra Soft strategically partnered with Mercury to provide a Linux Board Support Package for Cell, and support and development of software applications on various other Cell platforms, including the IBM BladeCenter JS21 and Cell QS20, and Mercury Cell-based solutions.[77] Terra Soft also maintains the Y-HPC (High Performance Computing) Cluster Construction and Management Suite and Y-Bio gene sequencing tools. Y-Bio is built upon the RPM Linux standard for package management, and offers tools which help bioinformatics researchers conduct their work with greater efficiency.[78] IBM has developed a pseudo-filesystem for Linux coined "Spufs" that simplifies access to and use of the SPE resources. IBM is currently maintaining a Linux kernel and GDB ports, while Sony maintains the GNU toolchain (GCC, binutils).[79]
In November 2005, IBM released a "Cell Broadband Engine (CBE) Software Development Kit Version 1.0", consisting of a simulator and assorted tools, to its web site. Development versions of the latest kernel and tools for Fedora Core 4 are maintained at the Barcelona Supercomputing Center website.[80]
In August 2007, Mercury Computer Systems released a Software Development Kit for PlayStation 3 for High-Performance Computing.[81]
In November 2007, Fixstars Corporation released the new "CVCell" module aiming to accelerate several important OpenCV APIs for Cell. In a series of software calculation tests, they recorded execution times on a 3.2 GHz Cell processor that were between 6x and 27x faster compared with the same software on a 2.4 GHz Intel Core 2 Duo.[82]
In October 2009, IBM released an OpenCL driver for POWER6 and CBE. This allows programs written in the cross-platform API to be easily run on Cell PSE.[83]
Gallery
Illustrations of the different generations of Cell/B.E. processors and the PowerXCell 8i. The images are not to scale; All Cell/B.E. packages measures 42.5×42.5 mm and the PowerXCell 8i measures 47.5×47.5 mm.
-
The 90 nm Cell/B.E. that shipped with the first PlayStation 3. The usual way one would see it is with its lid on, as it is glued on and not easily removed.
-
The 90 nm Cell/B.E. that shipped with the first PlayStation 3. It has its lid removed to show the size of the processor die underneath.
-
The underside of the 90 nm Cell/B.E. processor showing its 1242 solder balls, each 0.6 mm in diameter, and its array of 35 capacitors
-
The 65 nm Cell/B.E. that shipped with updated PlayStation 3s. It has its lid removed to show the size of the processor die underneath.
-
The 45 nm Cell/B.E. that shipped with updated PlayStation 3s such as the Slim and Super Slim versions. It has its lid removed to show the size of the processor die underneath.
-
The 65 nm high-performance PowerXCell 8i with extra capacitors on top due to decoupling needed for noise introduced by the DDR2 interface
See also
- STI Center of Competence for the Cell Processor
- Adapteva Epiphany architecture, a similar network-on-a-chip with local stores and DMA, but more cores and easier off-core communication.
- Vision Processing Unit, an emerging class of processor with some similar features
- Multiprocessor system on a chip
- Cell software development
- Xenon (processor)
- PowerPC
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External links
- Cell Broadband Engine resource center
- Sony Computer Entertainment Incorporated's Cell resource page
- Cmpware Configurable Multiprocessor Development Kit for Cell BE
- ISSCC 2005: The CELL Microprocessor, a comprehensive overview of the CELL microarchitecture
- Holy Chip!
- The little broadband engine that could
- Introducing the IBM/Sony/Toshiba Cell Processor — Part I: the SIMD processing units
- Introducing the IBM/Sony/Toshiba Cell Processor -- Part II: The Cell Architecture
- The Soul of Cell: An interview with Dr. H. Peter Hofstee