Fin field-effect transistor

Source: Wikipedia, the free encyclopedia.
(Redirected from
FinFET
)
A double-gate FinFET device

A fin field-effect transistor (FinFET) is a multigate device, a MOSFET (metal–oxide–semiconductor field-effect transistor) built on a substrate where the gate is placed on two, three, or four sides of the channel or wrapped around the channel, forming a double or even multi gate structure. These devices have been given the generic name "FinFETs" because the source/drain region forms fins on the silicon surface. The FinFET devices have significantly faster switching times and higher current density than planar CMOS (complementary metal–oxide–semiconductor) technology.[1]

FinFET is a type of non-planar

nodes
.

It is common for a single FinFET transistor to contain several fins, arranged side by side and all covered by the same gate, that act electrically as one. The number of fins can be varied to adjust drive strength and performance,[3] with drive strength increasing with a higher number of fins.[4]

History

After the MOSFET was first demonstrated by

gate electrodes connected together.[8][9]

The first FinFET transistor type was called a "Depleted Lean-channel Transistor" (DELTA) transistor, which was first fabricated in Japan by Hitachi Central Research Laboratory's Digh Hisamoto, Toru Kaga, Yoshifumi Kawamoto and Eiji Takeda in 1989.[8][10][11] The gate of the transistor can cover and electrically contact the semiconductor channel fin on both the top and the sides or only on the sides. The former is called a tri-gate transistor and the latter a double-gate transistor. A double-gate transistor optionally can have each side connected to two different terminal or contacts. This variant is called split transistor. This enables more refined control of the operation of the transistor.

Indonesian engineer Effendi Leobandung, while working at the

70 nm channel length.[12]

The potential of Digh Hisamoto's research on DELTA transistors drew the attention of the Defense Advanced Research Projects Agency (DARPA), which in 1997 awarded a contract to a research group at the University of California, Berkeley to develop a deep sub-micron transistor based on DELTA technology.[15] The group was led by Hisamoto along with TSMC's Chenming Hu. The team made the following breakthroughs between 1998 and 2004.[16]

They coined the term "FinFET" (fin field-effect transistor) in a December 2000 paper,[21] used to describe a non-planar, double-gate transistor built on an SOI substrate.[22]

In 2006, a team of Korean researchers from the

gate-all-around (GAA) FinFET technology.[23][24] In 2011, Rice University researchers Masoud Rostami and Kartik Mohanram demonstrated that FinFETs can have two electrically independent gates, which gives circuit designers more flexibility to design with efficient, low-power gates.[25]

In 2020, Chenming Hu received the IEEE Medal of Honor award for his development of the FinFET, which the Institute of Electrical and Electronics Engineers (IEEE) credited with taking transistors to the third dimension and extending Moore's law.[26]

Commercialization

The industry's first 25 nanometer transistor operating on just 0.7

gate delay of just 0.39 picosecond
(ps) for the N-type transistor and 0.88 ps for the P-type.

In 2004,

90 nm Bulk FinFET process.[16]

In 2011,

tri-gate transistors, where the gate surrounds the channel on three sides, allowing for increased energy efficiency and lower gate delay—and thus greater performance—over planar transistors.[27][28][29]

Commercially produced chips at

14 nm (or 16 nm) major foundries (TSMC, Samsung, GlobalFoundries
) utilised FinFET designs.

In 2013,

GAAFET process by 2021.[36] FD-SOI (Fully Depleted Silicon On Insulator) has been seen as a potential low cost alternative to FinFETs.[37]


Commercial production of

10 nm multi-level cell (MLC) NAND flash memory.[33] In 2017, TSMC began production of SRAM memory using a 7 nm process.[34]

See also

References

  1. ^
    S2CID 249074588
    . Retrieved 2022-05-26.
  2. ^ "What is Finfet?". Computer Hope. April 26, 2017. Retrieved 4 July 2019.
  3. ^ Shimpi, Anand Lal (4 May 2011). "Intel Announces first 22nm 3D Tri-Gate Transistors, Shipping in 2H 2011". AnandTech. Retrieved 18 January 2022.
  4. ^ "VLSI Symposium - TSMC and Imec on Advanced Process and Devices Technology Toward 2nm". 25 February 2024.
  5. ^ "1960: Metal Oxide Semiconductor (MOS) Transistor Demonstrated". The Silicon Engine. Computer History Museum. Retrieved 25 September 2019.
  6. .
  7. .
  8. ^ .
  9. .
  10. .
  11. ^ "IEEE Andrew S. Grove Award Recipients". IEEE Andrew S. Grove Award. Institute of Electrical and Electronics Engineers. Retrieved 4 July 2019.
  12. ^
    S2CID 30066882
    .
  13. ^ Leobandung, Effendi (June 1996). Nanoscale MOSFETs and single charge transistors on SOI (Ph.D. thesis). Minneapolis, Minnesota: University of Minnesota. p. 72.
  14. ISSN 1071-1023
    .
  15. ^ "The Breakthrough Advantage for FPGAs with Tri-Gate Technology" (PDF). Intel. 2014. Retrieved 4 July 2019.
  16. ^ a b Tsu-Jae King, Liu (June 11, 2012). "FinFET: History, Fundamentals and Future". University of California, Berkeley. Symposium on VLSI Technology Short Course. Archived from the original on 28 May 2016. Retrieved 9 July 2019.
  17. S2CID 37774589
    .
  18. .
  19. .
  20. .
  21. .
  22. .
  23. ^ "Still Room at the Bottom.(nanometer transistor developed by Yang-kyu Choi from the Korea Advanced Institute of Science and Technology )", Nanoparticle News, 1 April 2006, archived from the original on 6 November 2012, retrieved 6 July 2019
  24. S2CID 26482358
    .
  25. .
  26. ^ "How the Father of FinFETs Helped Save Moore's Law: Chenming Hu, the 2020 IEEE Medal of Honor recipient, took transistors into the third dimension". IEEE Spectrum. 21 April 2020. Retrieved 27 December 2021.
  27. ^ Bohr, Mark; Mistry, Kaizad (May 2011). "Intel's Revolutionary 22 nm Transistor Technology" (PDF). intel.com. Retrieved April 18, 2018.
  28. ^ Grabham, Dan (May 6, 2011). "Intel's Tri-Gate transistors: everything you need to know". TechRadar. Retrieved April 19, 2018.
  29. ^ Bohr, Mark T.; Young, Ian A. (2017). "CMOS Scaling Trends and Beyond". IEEE Micro. 37 (6): 20–29.
    S2CID 6700881
    . The next major transistor innovation was the introduction of FinFET (tri-gate) transistors on Intel's 22-nm technology in 2011.
  30. ^ "Intel 22nm 3-D Tri-Gate Transistor Technology". Intel Newsroom.
  31. ^ a b "History: 2010s". SK Hynix. Retrieved 8 July 2019.
  32. ^ "16/12nm Technology". TSMC. Retrieved 30 June 2019.
  33. ^ a b "Samsung Mass Producing 128Gb 3-bit MLC NAND Flash". Tom's Hardware. 11 April 2013. Retrieved 21 June 2019.
  34. ^ a b "7nm Technology". TSMC. Retrieved 30 June 2019.
  35. ^ Shilov, Anton. "Samsung Completes Development of 5nm EUV Process Technology". www.anandtech.com. Retrieved 2019-05-31.
  36. ^ Armasu, Lucian (11 January 2019), "Samsung Plans Mass Production of 3nm GAAFET Chips in 2021", www.tomshardware.com
  37. ^ "Samsung, GF Ramp FD-SOI". 27 April 2018.

External links

This page is based on the copyrighted Wikipedia article: FinFET. Articles is available under the CC BY-SA 3.0 license; additional terms may apply.Privacy Policy