Flash memory
Computer memory and Computer data storage types |
---|
Volatile |
Non-volatile |
Flash memory is an
Flash memory, a type of
The NAND type is found mainly in
NOR Flash is known for its direct random access capabilities, making it apt for executing code directly. Its architecture allows for individual byte access, facilitating faster read speeds compared to NAND Flash. NAND Flash memory operates with a different architecture, relying on a serial access approach. This makes NAND suitable for high-density data storage but less efficient for random access tasks. NAND Flash is often employed in scenarios where cost-effective, high-capacity storage is crucial, such as in USB drives, memory cards, and solid-state drives (SSDs).
The primary differentiator lies in their use cases and internal structures. NOR Flash is optimal for applications requiring quick access to individual bytes, like in embedded systems for program execution. NAND Flash, on the other hand, shines in scenarios demanding cost-effective, high-capacity storage with sequential data access.
Flash memory
Because erase cycles are slow, the large block sizes used in flash memory erasing give it a significant speed advantage over non-flash EEPROM when writing large amounts of data. As of 2019,[update] flash memory costs greatly less than byte-programmable EEPROM and had become the dominant memory type wherever a system required a significant amount of non-volatile solid-state storage. EEPROMs, however, are still used in applications that require only small amounts of storage, as in serial presence detect.[5][6]
Flash memory packages can use
History
Background
The origins of flash memory can be traced back to the development of the
Early types of floating-gate memory included EPROM (erasable PROM) and EEPROM (electrically erasable PROM) in the 1970s.
Invention and commercialization
Fujio Masuoka, while working for Toshiba, proposed a new type of floating-gate memory that allowed entire sections of memory to be erased quickly and easily, by applying a voltage to a single wire connected to a group of cells.[11] This led to Masuoka's invention of flash memory at Toshiba in 1980.[15][17][18] According to Toshiba, the name "flash" was suggested by Masuoka's colleague, Shōji Ariizumi, because the erasure process of the memory contents reminded him of the flash of a camera.[19] Masuoka and colleagues presented the invention of NOR flash in 1984,[20][21] and then NAND flash at the IEEE 1987 International Electron Devices Meeting (IEDM) held in San Francisco.[22]
Toshiba commercially launched NAND flash memory in 1987.
NAND flash has reduced erase and write times, and requires less chip area per cell, thus allowing greater storage density and lower cost per bit than NOR flash. However, the I/O interface of NAND flash does not provide a random-access external address bus. Rather, data must be read on a block-wise basis, with typical block sizes of hundreds to thousands of bits. This makes NAND flash unsuitable as a drop-in replacement for program ROM, since most microprocessors and microcontrollers require byte-level random access. In this regard, NAND flash is similar to other secondary
The first NAND-based removable memory card format was
Later developments
A new generation of memory card formats, including
NAND flash has achieved significant levels of memory
NOR flash was the most common type of Flash memory sold until 2005, when NAND flash overtook NOR flash in sales.[27]
Charge trap flash
Charge trap flash (CTF) technology replaces the polysilicon floating gate, which is sandwiched between a blocking gate oxide above and a tunneling oxide below it, with an electrically insulating silicon nitride layer; the silicon nitride layer traps electrons. In theory, CTF is less prone to electron leakage, providing improved data retention.[33][34][35][36][37][38]
Because CTF replaces the polysilicon with an electrically insulating nitride, it allows for smaller cells and higher endurance (lower degradation or wear). However, electrons can become trapped and accumulate in the nitride, leading to degradation. Leakage is exacerbated at high temperatures since electrons become more excited with increasing temperatures. CTF technology however still uses a tunneling oxide and blocking layer which are the weak points of the technology, since they can still be damaged in the usual ways (the tunnel oxide can be degraded due to extremely high electric fields and the blocking layer due to Anode Hot Hole Injection (AHHI).[39][40]
Degradation or wear of the oxides is the reason why flash memory has limited endurance, and data retention goes down (the potential for data loss increases) with increasing degradation, since the oxides lose their electrically insulating characteristics as they degrade. The oxides must insulate against electrons to prevent them from leaking which would cause data loss.
In 1991,
3D integrated circuit technology
In 2016, Micron and Intel introduced a technology known as CMOS Under the Array/CMOS Under Array (CUA), Core over Periphery (COP), Periphery Under Cell (PUA), or Xtacking,[52] in which the control circuitry for the flash memory is placed under or above the flash memory cell array. This has allowed for an increase in the number of planes or sections a flash memory chip has, increasing from 2 planes to 4, without increasing the area dedicated to the control or periphery circuitry. This increases the number of IO operations per flash chip or die, but it also introduces challenges when building capacitors for charge pumps used to write to the flash memory.[53][54][55] Some flash dies have as many as 8 planes.[56]
As of August 2017, microSD cards with a capacity up to 400 GB (400 billion bytes) are available.[57][58] The same year, Samsung combined 3D IC chip stacking with its 3D V-NAND and TLC technologies to manufacture its 512 GB KLUFG8R1EM flash memory chip with eight stacked 64-layer V-NAND chips.[8] In 2019, Samsung produced a 1024 GB flash chip, with eight stacked 96-layer V-NAND chips and with QLC technology.[59][60]
Principles of operation
Flash memory stores information in an array of memory cells made from
The floating gate may be conductive (typically polysilicon in most kinds of flash memory) or non-conductive (as in SONOS flash memory).[61]
Floating-gate MOSFET
In flash memory, each memory cell resembles a standard
Floating gate MOSFETs are so named because there is an electrically insulating tunnel oxide layer between the floating gate and the silicon, so the gate "floats" above the silicon. The oxide keeps the electrons confined to the floating gate. Degradation or wear (and the limited endurance of floating gate Flash memory) occurs due to the extremely high electric field (10 million volts per centimeter) experienced by the oxide. Such high voltage densities can break atomic bonds over time in the relatively thin oxide, gradually degrading its electrically insulating properties and allowing electrons to be trapped in and pass through freely (leak) from the floating gate into the oxide, increasing the likelihood of data loss since the electrons (the quantity of which is used to represent different charge levels, each assigned to a different combination of bits in MLC Flash) are normally in the floating gate. This is why data retention goes down and the risk of data loss increases with increasing degradation.[62][63][37][64][65] The silicon oxide in a cell degrades with every erase operation. The degradation increases the amount of negative charge in the cell over time due to trapped electrons in the oxide and negates some of the control gate voltage, this over time also makes erasing the cell slower, so to maintain the performance and reliability of the NAND chip, the cell must be retired from use. Endurance also decreases with the number of bits in a cell. With more bits in a cell, the number of possible states (each represented by a different voltage level) in a cell increases and is more sensitive to the voltages used for programming. Voltages may be adjusted to compensate for degradation of the silicon oxide, and as the number of bits increases, the number of possible states also increases and thus the cell is less tolerant of adjustments to programming voltages, because there is less space between the voltage levels that define each state in a cell.[66]
Fowler–Nordheim tunneling
The process of moving electrons from the control gate and into the floating gate is called
Internal charge pumps
Despite the need for relatively high programming and erasing voltages, virtually all flash chips today require only a single supply voltage and produce the high voltages that are required using on-chip charge pumps.
Over half the energy used by a 1.8 V NAND flash chip is lost in the charge pump itself. Since boost converters are inherently more efficient than charge pumps, researchers developing low-power SSDs have proposed returning to the dual Vcc/Vpp supply voltages used on all early flash chips, driving the high Vpp voltage for all flash chips in an SSD with a single shared external boost converter.[68][69][70][71][72][73][74][75]
In spacecraft and other high-radiation environments, the on-chip charge pump is the first part of the flash chip to fail, although flash memories will continue to work – in read-only mode – at much higher radiation levels.[76]
NOR flash
In NOR flash, each cell has one end connected directly to ground, and the other end connected directly to a bit line. This arrangement is called "NOR flash" because it acts like a NOR gate: when one of the word lines (connected to the cell's CG) is brought high, the corresponding storage transistor acts to pull the output bit line low. NOR flash continues to be the technology of choice for embedded applications requiring a discrete non-volatile memory device.[citation needed] The low read latencies characteristic of NOR devices allow for both direct code execution and data storage in a single memory product.[77]
Programming
A single-level NOR flash cell in its default state is logically equivalent to a binary "1" value, because current will flow through the channel under application of an appropriate voltage to the control gate, so that the bitline voltage is pulled down. A NOR flash cell can be programmed, or set to a binary "0" value, by the following procedure:
- an elevated on-voltage (typically >5 V) is applied to the CG
- the channel is now turned on, so electrons can flow from the source to the drain (assuming an NMOS transistor)
- the source-drain current is sufficiently high to cause some high energy electrons to jump through the insulating layer onto the FG, via a process called hot-electron injection.
Erasing
To erase a NOR flash cell (resetting it to the "1" state), a large voltage of the opposite polarity is applied between the CG and source terminal, pulling the electrons off the FG through
NAND flash
NAND flash also uses floating-gate transistors, but they are connected in a way that resembles a NAND gate: several transistors are connected in series, and the bit line is pulled low only if all the word lines are pulled high (above the transistors' VT). These groups are then connected via some additional transistors to a NOR-style bit line array in the same way that single transistors are linked in NOR flash.
Compared to NOR flash, replacing single transistors with serial-linked groups adds an extra level of addressing. Whereas NOR flash might address memory by page then word, NAND flash might address it by page, word and bit. Bit-level addressing suits bit-serial applications (such as hard disk emulation), which access only one bit at a time. Execute-in-place applications, on the other hand, require every bit in a word to be accessed simultaneously. This requires word-level addressing. In any case, both bit and word addressing modes are possible with either NOR or NAND flash.
To read data, first the desired group is selected (in the same way that a single transistor is selected from a NOR array). Next, most of the word lines are pulled up above VT2, while one of them is pulled up to VI. The series group will conduct (and pull the bit line low) if the selected bit has not been programmed.
Despite the additional transistors, the reduction in ground wires and bit lines allows a denser layout and greater storage capacity per chip. (The ground wires and bit lines are actually much wider than the lines in the diagrams.) In addition, NAND flash is typically permitted to contain a certain number of faults (NOR flash, as is used for a BIOS ROM, is expected to be fault-free). Manufacturers try to maximize the amount of usable storage by shrinking the size of the transistors or cells, however the industry can avoid this and achieve higher storage densities per die by using 3D NAND, which stacks cells on top of each other.
NAND Flash cells are read by analysing their response to various voltages.[64]
Writing and erasing
NAND flash uses
The hierarchical structure of NAND flash starts at a cell level which establishes strings, then pages, blocks, planes and ultimately a die. A string is a series of connected NAND cells in which the source of one cell is connected to the drain of the next one. Depending on the NAND technology, a string typically consists of 32 to 128 NAND cells. Strings are organised into pages which are then organised into blocks in which each string is connected to a separate line called a bitline. All cells with the same position in the string are connected through the control gates by a wordline. A plane contains a certain number of blocks that are connected through the same bitline. A flash die consists of one or more planes, and the peripheral circuitry that is needed to perform all the read, write, and erase operations.
The architecture of NAND flash means that data can be read and programmed (written) in pages, typically between 4 KiB and 16 KiB in size, but can only be erased at the level of entire blocks consisting of multiple pages. When a block is erased, all the cells are logically set to 1. Data can only be programmed in one pass to a page in a block that was erased. Any cells that have been set to 0 by programming can only be reset to 1 by erasing the entire block. This means that before new data can be programmed into a page that already contains data, the current contents of the page plus the new data must be copied to a new, erased page. If a suitable erased page is available, the data can be written to it immediately. If no erased page is available, a block must be erased before copying the data to a page in that block. The old page is then marked as invalid and is available for erasing and reuse.[82]
Vertical NAND
Vertical NAND (V-NAND) or 3D NAND memory stacks memory cells vertically and uses a charge trap flash architecture. The vertical layers allow larger areal bit densities without requiring smaller individual cells.[83] It is also sold under the trademark BiCS Flash, which is a trademark of Kioxia Corporation (formerly Toshiba Memory Corporation). 3D NAND was first announced by Toshiba in 2007.[45] V-NAND was first commercially manufactured by Samsung Electronics in 2013.[46][47][84][85]
Structure
V-NAND uses a charge trap flash geometry (which was commercially introduced in 2002 by AMD and Fujitsu)[44] that stores charge on an embedded silicon nitride film. Such a film is more robust against point defects and can be made thicker to hold larger numbers of electrons. V-NAND wraps a planar charge trap cell into a cylindrical form.[83] As of 2020, 3D NAND Flash memories by Micron and Intel instead use floating gates, however, Micron 128 layer and above 3D NAND memories use a conventional charge trap structure, due to the dissolution of the partnership between Micron and Intel. Charge trap 3D NAND Flash is thinner than floating gate 3D NAND. In floating gate 3D NAND, the memory cells are completely separated from one another, whereas in charge trap 3D NAND, vertical groups of memory cells share the same silicon nitride material.[86]
An individual memory cell is made up of one planar polysilicon layer containing a hole filled by multiple concentric vertical cylinders. The hole's polysilicon surface acts as the gate electrode. The outermost silicon dioxide cylinder acts as the gate dielectric, enclosing a silicon nitride cylinder that stores charge, in turn enclosing a silicon dioxide cylinder as the tunnel dielectric that surrounds a central rod of conducting polysilicon which acts as the conducting channel.[83]
Memory cells in different vertical layers do not interfere with each other, as the charges cannot move vertically through the silicon nitride storage medium, and the electric fields associated with the gates are closely confined within each layer. The vertical collection is electrically identical to the serial-linked groups in which conventional NAND flash memory is configured.[83] There is also string stacking, which builds several 3D NAND memory arrays or "plugs"[87] separately, but stacked together to create a product with a higher number of 3D NAND layers on a single die. Often, two or 3 arrays are stacked. The misalignment between plugs is in the order of 30 to 10nm.[53][88][56]
Construction
Growth of a group of V-NAND cells begins with an alternating stack of conducting (doped) polysilicon layers and insulating silicon dioxide layers.[83]
The next step is to form a cylindrical hole through these layers. In practice, a 128
Performance
As of 2013,[update] V-NAND flash architecture allows read and write operations twice as fast as conventional NAND and can last up to 10 times as long, while consuming 50 percent less power. They offer comparable physical bit density using 10-nm lithography but may be able to increase bit density by up to two orders of magnitude, given V-NAND's use of up to several hundred layers.[83] As of 2020, V-NAND chips with 160 layers are under development by Samsung.[89]
Cost
The wafer cost of a 3D NAND is comparable with scaled down (32 nm or less) planar NAND Flash.[90] However, with planar NAND scaling stopping at 16 nm, the cost per bit reduction can continue by 3D NAND starting with 16 layers. However, due to the non-vertical sidewall of the hole etched through the layers; even a slight deviation leads to a minimum bit cost, i.e., minimum equivalent design rule (or maximum density), for a given number of layers; this minimum bit cost layer number decreases for smaller hole diameter.[91]
Limitations
Block erasure
One limitation of flash memory is that it can be erased only a block at a time. This generally sets all bits in the block to 1. Starting with a freshly erased block, any location within that block can be programmed. However, once a bit has been set to 0, only by erasing the entire block can it be changed back to 1. In other words, flash memory (specifically NOR flash) offers random-access read and programming operations but does not offer arbitrary random-access rewrite or erase operations. A location can, however, be rewritten as long as the new value's 0 bits are a superset of the over-written values. For example, a nibble value may be erased to 1111, then written as 1110. Successive writes to that nibble can change it to 1010, then 0010, and finally 0000. Essentially, erasure sets all bits to 1, and programming can only clear bits to 0.[92] Some file systems designed for flash devices make use of this rewrite capability, for example Yaffs1, to represent sector metadata. Other flash file systems, such as YAFFS2, never make use of this "rewrite" capability—they do a lot of extra work to meet a "write once rule".
Although data structures in flash memory cannot be updated in completely general ways, this allows members to be "removed" by marking them as invalid. This technique may need to be modified for multi-level cell devices, where one memory cell holds more than one bit.
Common flash devices such as
Data retention
Data stored on flash cells is steadily lost due to electron detrapping[
Memory wear
Another limitation is that flash memory has a finite number of program – erase cycles (typically written as P/E cycles).[94][95] Micron Technology and Sun Microsystems announced an SLC NAND flash memory chip rated for 1,000,000 P/E cycles on 17 December 2008.[96] Longer P/E cycles of Industrial SSDs speak for their endurance level and make them more reliable for Industrial usage.
The guaranteed cycle count may apply only to block zero (as is the case with
In December 2012, Taiwanese engineers from Macronix revealed their intention to announce at the 2012 IEEE International Electron Devices Meeting that they had figured out how to improve NAND flash storage read/write cycles from 10,000 to 100 million cycles using a "self-healing" process that used a flash chip with "onboard heaters that could anneal small groups of memory cells."[97] The built-in thermal annealing was to replace the usual erase cycle with a local high temperature process that not only erased the stored charge, but also repaired the electron-induced stress in the chip, giving write cycles of at least 100 million.[98] The result was to be a chip that could be erased and rewritten over and over, even when it should theoretically break down. As promising as Macronix's breakthrough might have been for the mobile industry, however, there were no plans for a commercial product featuring this capability to be released any time in the near future.[99]
Read disturb
The method used to read NAND flash memory can cause nearby cells in the same memory block to change over time (become programmed). This is known as read disturb. The threshold number of reads is generally in the hundreds of thousands of reads between intervening erase operations. If reading continually from one cell, that cell will not fail but rather one of the surrounding cells will on a subsequent read. To avoid the read disturb problem the flash controller will typically count the total number of reads to a block since the last erase. When the count exceeds a target limit, the affected block is copied over to a new block, erased, then released to the block pool. The original block is as good as new after the erase. If the flash controller does not intervene in time, however, a read disturb error will occur with possible data loss if the errors are too numerous to correct with an
X-ray effects
Most flash ICs come in
Some manufacturers are now making X-ray proof SD[105] and USB[106] memory devices.
Low-level access
The low-level interface to flash memory chips differs from those of other memory types such as
NOR memory has an external address bus for reading and programming. For NOR memory, reading and programming are random-access, and unlocking and erasing are block-wise. For NAND memory, reading and programming are page-wise, and unlocking and erasing are block-wise.
NOR memories
Reading from NOR flash is similar to reading from random-access memory, provided the address and data bus are mapped correctly. Because of this, most microprocessors can use NOR flash memory as
Bad block management is a relatively new feature in NOR chips. In older NOR devices not supporting bad block management, the software or device driver controlling the memory chip must correct for blocks that wear out, or the device will cease to work reliably.
The specific commands used to lock, unlock, program, or erase NOR memories differ for each manufacturer. To avoid needing unique driver software for every device made, special Common Flash Memory Interface (CFI) commands allow the device to identify itself and its critical operating parameters.
Besides its use as random-access ROM, NOR flash can also be used as a storage device, by taking advantage of random-access programming. Some devices offer read-while-write functionality so that code continues to execute even while a program or erase operation is occurring in the background. For sequential data writes, NOR flash chips typically have slow write speeds, compared with NAND flash.
Typical NOR flash does not need an
NAND memories
NAND flash architecture was introduced by Toshiba in 1989.
Typical block sizes include:
- 32 pages of 512+16 bytes each for a block size (effective) of 16 KiB
- 64 pages of 2,048+64 bytes each for a block size of 128 KiB[111]
- 64 pages of 4,096+128 bytes each for a block size of 256 KiB[112]
- 128 pages of 4,096+128 bytes each for a block size of 512 KiB.
Modern NAND flash may have erase block size between 1 MiB to 128 MiB. While reading and programming is performed on a page basis, erasure can only be performed on a block basis.[113]
NAND devices also require bad block management by the device driver software or by a separate controller chip. Some SD cards, for example, include controller circuitry to perform bad block management and wear leveling. When a logical block is accessed by high-level software, it is mapped to a physical block by the device driver or controller. A number of blocks on the flash chip may be set aside for storing mapping tables to deal with bad blocks, or the system may simply check each block at power-up to create a bad block map in RAM. The overall memory capacity gradually shrinks as more blocks are marked as bad.
NAND relies on ECC to compensate for bits that may spontaneously fail during normal device operation. A typical ECC will correct a one-bit error in each 2048 bits (256 bytes) using 22 bits of ECC, or a one-bit error in each 4096 bits (512 bytes) using 24 bits of ECC.[114] If the ECC cannot correct the error during read, it may still detect the error. When doing erase or program operations, the device can detect blocks that fail to program or erase and mark them bad. The data is then written to a different, good block, and the bad block map is updated.
Most NAND devices are shipped from the factory with some bad blocks. These are typically marked according to a specified bad block marking strategy. By allowing some bad blocks, manufacturers achieve far higher yields than would be possible if all blocks had to be verified to be good. This significantly reduces NAND flash costs and only slightly decreases the storage capacity of the parts.
When executing software from NAND memories,
NAND sacrifices the random-access and execute-in-place advantages of NOR. NAND is best suited to systems requiring high capacity data storage. It offers higher densities, larger capacities, and lower cost. It has faster erases, sequential writes, and sequential reads.
Standardization
A group called the Open NAND Flash Interface Working Group (ONFI) has developed a standardized low-level interface for NAND flash chips. This allows interoperability between conforming NAND devices from different vendors. The ONFI specification version 1.0[115] was released on 28 December 2006. It specifies:
- A standard physical interface (packages
- A standard command set for reading, writing, and erasing NAND flash chips
- A mechanism for self-identification (comparable to the serial presence detection feature of SDRAM memory modules)
The ONFI group is supported by major NAND flash manufacturers, including
Two major flash device manufacturers, Toshiba and Samsung, have chosen to use an interface of their own design known as Toggle Mode (and now Toggle). This interface isn't pin-to-pin compatible with the ONFI specification. The result is that a product designed for one vendor's devices may not be able to use another vendor's devices.[117]
A group of vendors, including Intel, Dell, and Microsoft, formed a Non-Volatile Memory Host Controller Interface (NVMHCI) Working Group.[118] The goal of the group is to provide standard software and hardware programming interfaces for nonvolatile memory subsystems, including the "flash cache" device connected to the PCI Express bus.
Distinction between NOR and NAND flash
NOR and NAND flash differ in two important ways:
- The connections of the individual memory cells are different.[119]
- The interface provided for reading and writing the memory is different; NOR allows random access[120] as it can be either byte-addressable or word-addressable, with words being for example 32 bits long,[121][122][123] while NAND allows only page access.[124]
NOR[125] and NAND flash get their names from the structure of the interconnections between memory cells.[citation needed] In NOR flash, cells are connected in parallel to the bit lines, allowing cells to be read and programmed individually.[126] The parallel connection of cells resembles the parallel connection of transistors in a CMOS NOR gate.[127] In NAND flash, cells are connected in series,[126] resembling a CMOS NAND gate. The series connections consume less space than parallel ones, reducing the cost of NAND flash.[126] It does not, by itself, prevent NAND cells from being read and programmed individually.[citation needed]
Each NOR flash cell is larger than a NAND flash cell – 10 F2 vs 4 F2 – even when using exactly the same semiconductor device fabrication and so each transistor, contact, etc. is exactly the same size – because NOR flash cells require a separate metal contact for each cell.[128][129]
Because of the series connection and removal of wordline contacts, a large grid of NAND flash memory cells will occupy perhaps only 60% of the area of equivalent NOR cells
The first GSM phones and many feature phones had NOR flash memory, from which processor instructions could be executed direcly in an execute in place architecture and allowed for short boot times. With smartphones, NAND flash memory was adopted as it has larger storage capacities and lower costs, but causes longer boot times because instructions cannot be read from it directly, and must be copied to RAM memory first before execution.[131]
Attribute | NAND | NOR |
---|---|---|
Main application | File storage | Code execution |
Storage capacity | High | Low |
Cost per bit | Low | |
Active power | Low | |
Standby power | Low | |
Write speed | Fast | |
Read speed | Fast | |
Execute in place[132] (XIP) | No | Yes |
Reliability | High |
Write endurance
The write endurance of SLC floating-gate NOR flash is typically equal to or greater than that of NAND flash, while MLC NOR and NAND flash have similar endurance capabilities. Examples of endurance cycle ratings listed in datasheets for NAND and NOR flash, as well as in storage devices using flash memory, are provided.[133]
Type of flash memory |
Endurance rating (erases per block) |
Example(s) of flash memory or storage device |
---|---|---|
SLC NAND |
50,000–100,000 | Samsung OneNAND KFW4G16Q2M, Toshiba SLC NAND Flash chips,[134][135][136][137][138] Transcend SD500, Fujitsu S26361-F3298 |
MLC NAND | 5,000–10,000 for medium-capacity; 1,000 to 3,000 for high-capacity[139] |
Samsung K9G8G08U0M (Example for medium-capacity applications), Memblaze PBlaze4,[140] ADATA SU900, Mushkin Reactor |
TLC NAND | 1,000 | Samsung SSD 840 |
QLC NAND | unknown | SanDisk X4 NAND flash SD cards[141][142][143][144] |
3D SLC NAND | >100,000 | Samsung Z-NAND[145] |
3D MLC NAND | 6,000–40,000 | Samsung SSD 850 PRO, Samsung SSD 845DC PRO,[146][147] Samsung 860 PRO |
3D TLC NAND | 1,500–5,000 | Samsung SSD 850 EVO, Samsung SSD 845DC EVO, Crucial MX300[148][149][150],Memblaze PBlaze5 900, Memblaze PBlaze5 700, Memblaze PBlaze5 910/916, Memblaze PBlaze5 510/516,[151][152][153][154] ADATA SX 8200 PRO (also being sold under "XPG Gammix" branding, model S11 PRO) |
3D QLC NAND | 100–1,500 | Samsung SSD 860 QVO SATA, Intel SSD 660p, Micron 5210 ION, Crucial P1, Samsung SSD BM991 NVMe[155][156][157][158][159][160][161][162] |
3D PLC NAND | unknown | In development by SK Hynix (formerly Intel)[163] and Kioxia (formerly Toshiba Memory).[139] |
SLC (floating- gate) NOR |
100,000–1,000,000 | Numonyx M58BW (Endurance rating of 100,000 erases per block); Spansion S29CD016J (Endurance rating of 1,000,000 erases per block) |
MLC (floating- gate) NOR |
100,000 | Numonyx J3 flash |
However, by applying certain algorithms and design paradigms such as
In order to compute the longevity of the NAND flash, one must account for the size of the memory chip, the type of memory (e.g. SLC/MLC/TLC), and use pattern. Industrial NAND and server NAND are in demand due to their capacity, longer endurance and reliability in sensitive environments.
As the number of bits per cell increases, performance and life of NAND flash may degrade, increasing random read times to 100μs for TLC NAND which is 4 times the time required in SLC NAND, and twice the time required in MLC NAND, for random reads.[66]
Flash file systems
Because of the particular characteristics of flash memory, it is best used with either a controller to perform wear leveling and error correction or specifically designed flash file systems, which spread writes over the media and deal with the long erase times of NOR flash blocks. The basic concept behind flash file systems is the following: when the flash store is to be updated, the file system will write a new copy of the changed data to a fresh block, remap the file pointers, then erase the old block later when it has time.
In practice, flash file systems are used only for
to perform wear leveling and error correction so use of a specific flash file system may not add benefit.Capacity
Multiple chips are often arrayed or die stacked to achieve higher capacities
Consumer flash storage devices typically are advertised with usable sizes expressed as a small integer power of two (2, 4, 8, etc.) and a conventional designation of megabytes (MB) or gigabytes (GB); e.g., 512 MB, 8 GB. This includes
The flash memory chips inside them are sized in strict binary multiples, but the actual total capacity of the chips is not usable at the drive interface. It is considerably larger than the advertised capacity in order to allow for distribution of writes (
In 2005, Toshiba and SanDisk developed a NAND flash chip capable of storing 1 GB of data using multi-level cell (MLC) technology, capable of storing two bits of data per cell. In September 2005, Samsung Electronics announced that it had developed the world's first 2 GB chip.[167]
In March 2006, Samsung announced flash hard drives with a capacity of 4 GB, essentially the same order of magnitude as smaller laptop hard drives, and in September 2006, Samsung announced an 8 GB chip produced using a 40 nm manufacturing process.[168] In January 2008, SanDisk announced availability of their 16 GB MicroSDHC and 32 GB SDHC Plus cards.[169][170]
More recent flash drives (as of 2012) have much greater capacities, holding 64, 128, and 256 GB.[171]
A joint development at Intel and Micron will allow the production of 32-layer 3.5 terabyte (TB[clarification needed]) NAND flash sticks and 10 TB standard-sized SSDs. The device includes 5 packages of 16 × 48 GB TLC dies, using a floating gate cell design.[172]
Flash chips continue to be manufactured with capacities under or around 1 MB (e.g. for BIOS-ROMs and embedded applications).
In July 2016, Samsung announced the 4 TB [clarification needed] Samsung 850 EVO which utilizes their 256 Gbit 48-layer TLC 3D V-NAND.[173] In August 2016, Samsung announced a 32 TB 2.5-inch SAS SSD based on their 512 Gbit 64-layer TLC 3D V-NAND. Further, Samsung expects to unveil SSDs with up to 100 TB of storage by 2020.[174]
Transfer rates
Flash memory devices are typically much faster at reading than writing.[175] Performance also depends on the quality of storage controllers, which become more critical when devices are partially full.[vague][175] Even when the only change to manufacturing is die-shrink, the absence of an appropriate controller can result in degraded speeds.[176]
Applications
Serial flash
Serial flash is a small, low-power flash memory that provides only serial access to the data - rather than addressing individual bytes, the user reads or writes large contiguous groups of bytes in the address space serially.
There are several reasons why a serial device, with fewer external pins than a parallel device, can significantly reduce overall cost:
- Many wire bond pads, rather than the complexity and number of gates used for the device logic. Eliminating bond pads thus permits a more compact integrated circuit, on a smaller die; this increases the number of dies that may be fabricated on a wafer, and thus reduces the cost per die.
- Reducing the number of external pins also reduces assembly and packagingcosts. A serial device may be packaged in a smaller and simpler package than a parallel device.
- Smaller and lower pin-count packages occupy less PCB area.
- Lower pin-count devices simplify PCB routing.
There are two major SPI flash types. The first type is characterized by small pages and one or more internal SRAM page buffers allowing a complete page to be read to the buffer, partially modified, and then written back (for example, the Atmel
The two types are not easily exchangeable, since they do not have the same pinout, and the command sets are incompatible.
Most
Firmware storage
With the increasing speed of modern CPUs, parallel flash devices are often much slower than the memory bus of the computer they are connected to. Conversely, modern
Flash memory as a replacement for hard drives
One more recent application for flash memory is as a replacement for
There remain some aspects of flash-based SSDs that make them unattractive. The cost per gigabyte of flash memory remains significantly higher than that of hard disks.
For relational databases or other systems that require ACID transactions, even a modest amount of flash storage can offer vast speedups over arrays of disk drives.[181]
In May 2006, Samsung Electronics announced two flash-memory based PCs, the Q1-SSD and Q30-SSD were expected to become available in June 2006, both of which used 32 GB SSDs, and were at least initially available only in South Korea.[182] The Q1-SSD and Q30-SSD launch was delayed and finally was shipped in late August 2006.[183]
The first flash-memory based PC to become available was the Sony Vaio UX90, announced for pre-order on 27 June 2006 and began to be shipped in Japan on 3 July 2006 with a 16Gb flash memory hard drive.[184] In late September 2006 Sony upgraded the flash-memory in the Vaio UX90 to 32Gb.[185]
A solid-state drive was offered as an option with the first MacBook Air introduced in 2008, and from 2010 onwards, all models were shipped with an SSD. Starting in late 2011, as part of Intel's Ultrabook initiative, an increasing number of ultra-thin laptops are being shipped with SSDs standard.
There are also hybrid techniques such as hybrid drive and ReadyBoost that attempt to combine the advantages of both technologies, using flash as a high-speed non-volatile cache for files on the disk that are often referenced, but rarely modified, such as application and operating system executable files.
Flash memory as RAM
As of 2012,[update] there are attempts to use flash memory as the main computer memory, DRAM.[186]
Archival or long-term storage
Floating-gate transistors in the flash storage device hold charge which represents data. This charge gradually leaks over time, leading to an accumulation of
Data retention
It is unclear how long data on flash memory will persist under archival conditions (i.e., benign temperature and humidity with infrequent access with or without prophylactic rewrite). Datasheets of Atmel's flash-based "
The retention span varies among types and models of flash storage. When supplied with power and idle, the charge of the transistors holding the data is routinely refreshed by the
An article from CMU in 2015 states "Today's flash devices, which do not require flash refresh, have a typical retention age of 1 year at room temperature." And that retention time decreases exponentially with increasing temperature. The phenomenon can be modeled by the Arrhenius equation.[190][191]
FPGA configuration
Some
Industry
One source states that, in 2008, the flash memory industry includes about US$9.1 billion in production and sales. Other sources put the flash memory market at a size of more than US$20 billion in 2006, accounting for more than eight percent of the overall semiconductor market and more than 34 percent of the total semiconductor memory market.[192] In 2012, the market was estimated at $26.8 billion.[193] It can take up to 10 weeks to produce a flash memory chip.[194]
Manufacturers
The following were the largest NAND flash memory manufacturers, as of the second quarter of 2023.[195]
- Samsung Electronics – 31.4%
- Kioxia – 20.6%
- Western Digital Corporation– 12.6%
- SK Hynix – 18.5%
- Micron Technology – 12.3%
- Others – 8.7% Note: SK Hynix acquired Intel's NAND business at the end of 2021[196] Kioxia spun out and got renamed of Toshiba in 2018/2019.[197]
Samsung remains the largest NAND flash memory manufacturer as of first quarter 2022.[198]
Shipments
Year(s) | Discrete flash memory chips
|
Flash memory data capacity ( gigabytes )
|
Floating-gate MOSFET memory cells (billions) |
---|---|---|---|
1992 | 26,000,000[199] | 3[199] | 24[a] |
1993 | 73,000,000[199] | 17[199] | 139[a] |
1994 | 112,000,000[199] | 25[199] | 203[a] |
1995 | 235,000,000[199] | 38[199] | 300[a] |
1996 | 359,000,000[199] | 140[199] | 1,121[a] |
1997 | 477,200,000+[200] | 317+[200] | 2,533+[a] |
1998 | 762,195,122[201] | 455+[200] | 3,642+[a] |
1999 | 12,800,000,000[202] | 635+[200] | 5,082+[a] |
2000–2004 | 134,217,728,000 (NAND)[203] | 1,073,741,824,000 (NAND)[203] | |
2005–2007 | ? | ||
2008 | 1,226,215,645 (mobile NAND)[204] | ||
2009 | 1,226,215,645+ (mobile NAND) | ||
2010 | 7,280,000,000+[b] | ||
2011 | 8,700,000,000[206] | ||
2012 | 5,151,515,152 (serial)[207] | ||
2013 | ? | ||
2014 | ? | 59,000,000,000[208] | 118,000,000,000+[a] |
2015 | 7,692,307,692 (NAND)[209] | 85,000,000,000[210] | 170,000,000,000+[a] |
2016 | ? | 100,000,000,000[211] | 200,000,000,000+[a] |
2017 | ? | 148,200,000,000[c] | 296,400,000,000+[a] |
2018 | ? | 231,640,000,000[d] | 463,280,000,000+[a] |
2019 | ? | ? | ? |
2020 | ? | ? | ? |
1992–2020 | 45,358,454,134+ memory chips | 758,057,729,630+ gigabytes | 2,321,421,837,044 billion+ cells |
In addition to individual flash memory chips, flash memory is also
Flash scalability
Due to its relatively simple structure and high demand for higher capacity, NAND flash memory is the most aggressively
ITRS or company | 2010 | 2011 | 2012 | 2013 | 2014 | 2015 | 2016 | 2017 | 2018 |
---|---|---|---|---|---|---|---|---|---|
ITRS Flash Roadmap 2011[218] | 32 nm |
22 nm |
20 nm | 18 nm | 16 nm | ||||
Updated ITRS Flash Roadmap[219] | 17 nm | 15 nm | 14 nm |
||||||
Samsung[218][219][220] (Samsung 3D NAND)[219] |
35–20 nm[32] | 27 nm | 21 nm ( TLC ) |
19–16 nm 19–10 nm (MLC, TLC)[221] |
19–10 nm V-NAND (24L) |
16–10 nm V-NAND (32L) |
16–10 nm | 12–10 nm | 12–10 nm |
Micron, Intel[218][219][220] | 34–25 nm | 25 nm | 20 nm (MLC + HKMG) |
20 nm (TLC) |
16 nm | 16 nm 3D NAND |
16 nm 3D NAND |
12 nm 3D NAND |
12 nm 3D NAND |
Toshiba, WD (SanDisk)[218][219][220] | 43–32 nm 24 nm (Toshiba)[222] |
24 nm | 19 nm (MLC, TLC) |
15 nm | 15 nm 3D NAND |
15 nm 3D NAND |
12 nm 3D NAND |
12 nm 3D NAND | |
SK Hynix[218][219][220] | 46–35 nm | 26 nm | 20 nm (MLC) | 16 nm | 16 nm | 16 nm | 12 nm | 12 nm |
As the
Timeline
Date of introduction | Chip name | Memory Package Capacity Megabits (Mb), Gigabits (Gb), Terabits (Tb) |
Flash type | Cell type | Layers or Stacks of Layers |
Manufacturer(s) | Process | Area | Ref |
---|---|---|---|---|---|---|---|---|---|
1984 | ? | ? | NOR | SLC | 1 | Toshiba | ? | ? | [20] |
1985 | ? | 256 kb | NOR | SLC | 1 | Toshiba | 2,000 nm | ? | [29] |
1987 | ? | ? | NAND | SLC | 1 | Toshiba | ? | ? | [1] |
1989 | ? | 1 Mb | NOR | SLC | 1 | Seeq, Intel | ? | ? | [29] |
4 Mb | NAND | SLC | 1 | Toshiba | 1,000 nm | ||||
1991 | ? | 16 Mb | NOR | SLC | 1 | Mitsubishi | 600 nm | ? | [29] |
1993 | DD28F032SA | 32 Mb | NOR | SLC | 1 | Intel | ? | 280 mm² | [225][226] |
1994 | ? | 64 Mb | NOR | SLC | 1 | NEC | 400 nm | ? | [29] |
1995 | ? | 16 Mb | DINOR | SLC | 1 | Mitsubishi, Hitachi | ? | ? | [29][227] |
NAND | SLC | 1 | Toshiba | ? | ? | [228] | |||
32 Mb | NAND | SLC | 1 | Hitachi, Samsung, Toshiba | ? | ? | [29] | ||
34 Mb | Serial | SLC | 1 | SanDisk | |||||
1996 | ? | 64 Mb | NAND | SLC | 1 | Hitachi, Mitsubishi | 400 nm | ? | [29] |
QLC | 1 | NEC | |||||||
128 Mb | NAND | SLC | 1 | Samsung, Hitachi | ? | ||||
1997 | ? | 32 Mb | NOR | SLC | 1 | Intel, Sharp | 400 nm | ? | [229] |
NAND | SLC | 1 | AMD, Fujitsu | 350 nm | |||||
1999 | ? | 256 Mb | NAND | SLC | 1 | Toshiba | 250 nm | ? | [29] |
MLC | 1 | Hitachi | 1 | ||||||
2000 | ? | 32 Mb | NOR | SLC | 1 | Toshiba | 250 nm | ? | [29] |
64 Mb | NOR | QLC | 1 | STMicroelectronics | 180 nm | ||||
512 Mb | NAND | SLC | 1 | Toshiba | ? | ? | [109] | ||
2001 | ? | 512 Mb | NAND | MLC | 1 | Hitachi | ? | ? | [29] |
1 Gibit | NAND | MLC | 1 | Samsung | |||||
1 | Toshiba, SanDisk | 160 nm | ? | [230] | |||||
2002 | ? | 512 Mb | NROM | MLC | 1 | Saifun | 170 nm | ? | [29] |
2 Gb | NAND | SLC | 1 | Samsung, Toshiba | ? | ? | [231][232] | ||
2003 | ? | 128 Mb | NOR | MLC | 1 | Intel | 130 nm | ? | [29] |
1 Gb | NAND | MLC | 1 | Hitachi | |||||
2004 | ? | 8 Gb | NAND | SLC | 1 | Samsung | 60 nm | ? | [231] |
2005 | ? | 16 Gb | NAND | SLC | 1 | Samsung | 50 nm | ? | [32] |
2006 | ? | 32 Gb | NAND | SLC | 1 | Samsung | 40 nm | ||
Apr-07 | THGAM | 128 Gb | Stacked NAND | SLC | Toshiba | 56 nm | 252 mm² | [48] | |
Sep-07 | ? | 128 Gb | Stacked NAND | SLC | Hynix | ? | ? | [49] | |
2008 | THGBM | 256 Gb | Stacked NAND | SLC | Toshiba | 43 nm | 353 mm² | [50] | |
2009 | ? | 32 Gb | NAND | TLC | Toshiba | 32 nm | 113 mm² | [30] | |
64 Gb | NAND | QLC | Toshiba, SanDisk | 43 nm | ? | [30][31] | |||
2010 | ? | 64 Gb | NAND | SLC | Hynix | 20 nm | ? | [233] | |
TLC | Samsung | 20 nm | ? | [32] | |||||
THGBM2 | 1 Tb | Stacked NAND | QLC | Toshiba | 32 nm | 374 mm² | [51] | ||
2011 | KLMCG8GE4A | 512 Gb | Stacked NAND | MLC | Samsung | ? | 192 mm² | [234] | |
2013 | ? | ? | NAND | SLC | SK Hynix | 16 nm | ? | [233] | |
128 Gb | V-NAND | TLC | Samsung | 10 nm | ? | ||||
2015 | ? | 256 Gb | V-NAND | TLC | Samsung | ? | ? | [221] | |
2017 | eUFS 2.1 | 512 Gb | V-NAND | TLC | 8 of 64 | Samsung | ? | ? | [8] |
768 Gb | V-NAND | QLC | Toshiba | ? | ? | [235] | |||
KLUFG8R1EM | 4 Tb | Stacked V-NAND | TLC | Samsung | ? | 150 mm² | [8] | ||
2018 | ? | 1 Tb | V-NAND | QLC | Samsung | ? | ? | [236] | |
1.33 Tb | V-NAND | QLC | Toshiba | ? | 158 mm² | [237][238] | |||
2019 | ? | 512 Gb | V-NAND | QLC | Samsung | ? | ? | [59][60] | |
1 Tb | V-NAND | TLC | SK Hynix | ? | ? | [239] | |||
eUFS 2.1 | 1 Tb | Stacked V-NAND[240] | QLC | 16 of 64 | Samsung | ? | 150 mm² | [59][60][241] | |
2023 | eUFS 4.0 | 8 Tb | 3D NAND | QLC | 232 | Micron | ? | ? | [242] |
See also
- eMMC
- Flash memory controller
- Intel hex file format
- List of flash file systems
- List of flash memory controller manufacturers
- TiB
- NOR flash replacement
- Open NAND Flash Interface Working Group
- Read-mostly memory (RMM)
- Universal Flash Storage
- USB flash drive security
- Write amplification
Explanatory notes
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External links
- Semiconductor Characterization System has diverse functions Archived 22 October 2018 at the Wayback Machine
- Understanding and selecting higher performance NAND architectures Archived 31 October 2012 at the Wayback Machine
- How flash storage works, presentation by David Woodhouse from Intel
- Flash endurance testing
- NAND Flash Data Recovery Cookbook
- Type of Flash Memory by OpenWrt