Instruction set architecture
Machine code |
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General concepts |
Instructions |
In computer science, an instruction set architecture (ISA) is an abstract model that generally defines how software controls the CPU in a computer or a family of computers.[1] A device or program that executes instructions described by that ISA, such as a central processing unit (CPU), is called an implementation of that ISA.
In general, an ISA defines the supported
model of implementations of the ISA.An ISA specifies the behavior of
If an operating system maintains a standard and compatible application binary interface (ABI) for a particular ISA, machine code will run on future implementations of that ISA and operating system. However, if an ISA supports running multiple operating systems, it does not guarantee that machine code for one operating system will run on another operating system, unless the first operating system supports running machine code built for the other operating system.
An ISA can be extended by adding instructions or other capabilities, or adding support for larger addresses and data values; an implementation of the extended ISA will still be able to execute machine code for versions of the ISA without those extensions. Machine code using those extensions will only run on implementations that support those extensions.
The binary compatibility that they provide makes ISAs one of the most fundamental abstractions in computing.
Overview
An instruction set architecture is distinguished from a
The concept of an architecture, distinct from the design of a specific machine, was developed by
Prior to NPL [System/360], the company's computer designers had been free to honor cost objectives not only by selecting technologies but also by fashioning functional and architectural refinements. The SPREAD compatibility objective, in contrast, postulated a single architecture for a series of five processors spanning a wide range of cost and performance. None of the five engineering design teams could count on being able to bring about adjustments in architectural specifications as a way of easing difficulties in achieving cost and performance objectives.[2]
Some
Classification of ISAs
An ISA may be classified in a number of different ways. A common classification is by architectural complexity. A complex instruction set computer (CISC) has many specialized instructions, some of which may only be rarely used in practical programs. A reduced instruction set computer (RISC) simplifies the processor by efficiently implementing only the instructions that are frequently used in programs, while the less common operations are implemented as subroutines, having their resulting additional processor execution time offset by infrequent use.[3]
Other types include very long instruction word (VLIW) architectures, and the closely related long instruction word (LIW)[citation needed] and explicitly parallel instruction computing (EPIC) architectures. These architectures seek to exploit instruction-level parallelism with less hardware than RISC and CISC by making the compiler responsible for instruction issue and scheduling.[4]
Architectures with even less complexity have been studied, such as the minimal instruction set computer (MISC) and one-instruction set computer (OISC). These are theoretically important types, but have not been commercialized.[5][6]
Instructions
Machine language is built up from discrete statements or instructions. On the processing architecture, a given instruction may specify:
- opcode (the instruction to be performed) e.g. add, copy, test
- any explicit operands:
- registers
- literal/constant values
- addressing modes used to access memory
More complex operations are built up by combining these simple instructions, which are executed sequentially, or as otherwise directed by control flow instructions.
Instruction types
Examples of operations common to many instruction sets include:
Data handling and memory operations
- Set a register to a fixed constant value.
- Copy data from a memory location or a register to a memory location or a register (a machine instruction is often called move; however, the term is misleading). They are used to store the contents of a register, the contents of another memory location or the result of a computation, or to retrieve stored data to perform a computation on it later. They are often called load and storeoperations.
- Read and write data from hardware devices.
Arithmetic and logic operations
- Add, subtract, multiply, or divide the values of two registers, placing the result in a register, possibly setting one or more condition codes in a status register.[7]
- increment, decrement in some ISAs, saving operand fetch in trivial cases.
- Perform negationof each bit in a register.
- Compare two values in registers (for example, to see if one is less, or if they are equal).
- Floating-point instructions for arithmetic on floating-point numbers.[7]
Control flow operations
- Branch to another location in the program and execute instructions there.
- Conditionally branchto another location if a certain condition holds.
- Indirectly branch to another location.
- Callanother block of code, while saving the location of the next instruction as a point to return to.
Coprocessor instructions
- Load/store data to and from a coprocessor or exchanging with CPU registers.
- Perform coprocessor operations.
Complex instructions
Processors may include "complex" instructions in their instruction set. A single "complex" instruction does something that may take many instructions on other computers. Such instructions are
- transferring multiple registers to or from memory (especially the stack) at once
- moving large blocks of memory (e.g. DMA transfer)
- complicated integer and cosine, etc.)
- SIMD registers
- performing an atomic atomic instruction
- instructions that perform ALU operations with an operand from memory rather than a register
Complex instructions are more common in CISC instruction sets than in RISC instruction sets, but RISC instruction sets may include them as well. RISC instruction sets generally do not include ALU operations with memory operands, or instructions to move large blocks of memory, but most RISC instruction sets include
Instruction encoding
On traditional architectures, an instruction includes an opcode that specifies the operation to perform, such as add contents of memory to register—and zero or more operand specifiers, which may specify registers, memory locations, or literal data. The operand specifiers may have addressing modes determining their meaning or may be in fixed fields. In very long instruction word (VLIW) architectures, which include many microcode architectures, multiple simultaneous opcodes and operands are specified in a single instruction.
Some exotic instruction sets do not have an opcode field, such as transport triggered architectures (TTA), only operand(s).
Most
Conditional instructions often have a predicate field—a few bits that encode the specific condition to cause an operation to be performed rather than not performed. For example, a conditional branch instruction will transfer control if the condition is true, so that execution proceeds to a different part of the program, and not transfer control if the condition is false, so that execution continues sequentially. Some instruction sets also have conditional moves, so that the move will be executed, and the data stored in the target location, if the condition is true, and not executed, and the target location not modified, if the condition is false. Similarly, IBM
Number of operands
Instruction sets may be categorized by the maximum number of operands explicitly specified in instructions.
(In the examples that follow, a, b, and c are (direct or calculated) addresses referring to memory cells, while reg1 and so on refer to machine registers.)
C = A+B
- 0-operand (zero-address machines), so called stack machines: All arithmetic operations take place using the top one or two positions on the stack:[9]
push a
,push b
,add
,pop c
.C = A+B
needs four instructions.[10] For stack machines, the terms "0-operand" and "zero-address" apply to arithmetic instructions, but not to all instructions, as 1-operand push and pop instructions are used to access memory.
- 1-operand (one-address machines), so called accumulator machines, include early computers and many small microcontrollers: most instructions specify a single right operand (that is, constant, a register, or a memory location), with the implicit accumulatoras the left operand (and the destination if there is one):
load a
,add b
,store c
.C = A+B
needs three instructions.[10]
- 2-operand — many CISC and RISC machines fall under this category:
- CISC —
move A
to C; thenadd B
to C.C = A+B
needs two instructions. This effectively 'stores' the result without an explicit store instruction.
- CISC — Often machines are limited to one memory operand per instruction:
load a,reg1
;add b,reg1
;store reg1,c
; This requires a load/store pair for any memory movement regardless of whether theadd
result is an augmentation stored to a different place, as inC = A+B
, or the same memory location:A = A+B
.C = A+B
needs three instructions.
- RISC — Requiring explicit memory loads, the instructions would be:
load a,reg1
;load b,reg2
;add reg1,reg2
;store reg2,c
.C = A+B
needs four instructions.
- CISC —
- 3-operand, allowing better reuse of data:[11]
- CISC — It becomes either a single instruction:
add a,b,c
C = A+B
needs one instruction.
- CISC — Or, on machines limited to two memory operands per instruction,
move a,reg1
;add reg1,b,c
;C = A+B
needs two instructions.
- RISC — arithmetic instructions use registers only, so explicit 2-operand load/store instructions are needed:
load a,reg1
;load b,reg2
;add reg1+reg2->reg3
;store reg3,c
;C = A+B
needs four instructions.- Unlike 2-operand or 1-operand, this leaves all three values a, b, and c in registers available for further reuse.[11]
- CISC — It becomes either a single instruction:
- more operands—some CISC machines permit a variety of addressing modes that allow more than 3 operands (registers or memory accesses), such as the VAX "POLY" polynomial evaluation instruction.
Due to the large number of bits needed to encode the three registers of a 3-operand instruction, RISC architectures that have 16-bit instructions are invariably 2-operand designs, such as the Atmel AVR,
Each instruction specifies some number of operands (registers, memory locations, or immediate values) explicitly. Some instructions give one or both operands implicitly, such as by being stored on top of the
Register pressure
Register pressure measures the availability of free registers at any point in time during the program execution. Register pressure is high when a large number of the available registers are in use; thus, the higher the register pressure, the more often the register contents must be
While embedded instruction sets such as
Instruction length
The size or length of an instruction varies widely, from as little as four bits in some
Fixed-length instructions are less complicated to handle than variable-length instructions for several reasons (not having to check whether an instruction straddles a cache line or virtual memory page boundary,[11] for instance), and are therefore somewhat easier to optimize for speed.
Code density
In early 1960s computers, main memory was expensive and very limited, even on mainframes. Minimizing the size of a program to make sure it would fit in the limited memory was often central. Thus the size of the instructions needed to perform a particular task, the code density, was an important characteristic of any instruction set. It remained important on the initially-tiny memories of minicomputers and then microprocessors. Density remains important today, for smartphone applications, applications downloaded into browsers over slow Internet connections, and in ROMs for embedded applications. A more general advantage of increased density is improved effectiveness of caches and instruction prefetch.
Computers with high code density often have complex instructions for procedure entry, parameterized returns, loops, etc. (therefore retroactively named Complex Instruction Set Computers, CISC). However, more typical, or frequent, "CISC" instructions merely combine a basic ALU operation, such as "add", with the access of one or more operands in memory (using addressing modes such as direct, indirect, indexed, etc.). Certain architectures may allow two or three operands (including the result) directly in memory or may be able to perform functions such as automatic pointer increment, etc. Software-implemented instruction sets may have even more complex and powerful instructions.
Reduced instruction-set computers, RISC, were first widely implemented during a period of rapidly growing memory subsystems. They sacrifice code density to simplify implementation circuitry, and try to increase performance via higher clock frequencies and more registers. A single RISC instruction typically performs only a single operation, such as an "add" of registers or a "load" from a memory location into a register. A RISC instruction set normally has a fixed instruction length, whereas a typical CISC instruction set has instructions of widely varying length. However, as RISC computers normally require more and often longer instructions to implement a given task, they inherently make less optimal use of bus bandwidth and cache memories.
Certain embedded RISC ISAs like
There has been research into executable compression as a mechanism for improving code density. The mathematics of Kolmogorov complexity describes the challenges and limits of this.
In practice, code density is also dependent on the
Representation
The instructions constituting a program are rarely specified using their internal, numeric form (machine code); they may be specified by programmers using an assembly language or, more commonly, may be generated from high-level programming languages by compilers.[17]
Design
The design of instruction sets is a complex issue. There were two stages in history for the microprocessor. The first was the CISC (Complex Instruction Set Computer), which had many different instructions. In the 1970s, however, places like IBM did research and found that many instructions in the set could be eliminated. The result was the RISC (Reduced Instruction Set Computer), an architecture that uses a smaller set of instructions. A simpler instruction set may offer the potential for higher speeds, reduced processor size, and reduced power consumption. However, a more complex set may optimize common operations, improve memory and cache efficiency, or simplify programming.
Some instruction set designers reserve one or more opcodes for some kind of
Fast virtual machines are much easier to implement if an instruction set meets the Popek and Goldberg virtualization requirements.[clarification needed]
The NOP slide used in immunity-aware programming is much easier to implement if the "unprogrammed" state of the memory is interpreted as a NOP.[dubious ]
On systems with multiple processors,
Instruction set implementation
A given instruction set can be implemented in a variety of ways. All ways of implementing a particular instruction set provide the same programming model, and all implementations of that instruction set are able to run the same executables. The various ways of implementing an instruction set give different tradeoffs between cost, performance, power consumption, size, etc.
When designing the microarchitecture of a processor, engineers use blocks of "hard-wired" electronic circuitry (often designed separately) such as adders, multiplexers, counters, registers, ALUs, etc. Some kind of register transfer language is then often used to describe the decoding and sequencing of each instruction of an ISA using this physical microarchitecture. There are two basic ways to build a control unit to implement this description (although many designs use middle ways or compromises):
- Some computer designs "hardwire" the complete instruction set decoding and sequencing (just like the rest of the microarchitecture).
- Other designs employ writable control store), PLAs, or both.
Some microcoded CPU designs with a writable control store use it to allow the instruction set to be changed (for example, the Rekursiv processor and the Imsys Cjip).[19]
CPUs designed for reconfigurable computing may use field-programmable gate arrays (FPGAs).
An ISA can also be emulated in software by an interpreter. Naturally, due to the interpretation overhead, this is slower than directly running programs on the emulated hardware, unless the hardware running the emulator is an order of magnitude faster. Today, it is common practice for vendors of new ISAs or microarchitectures to make software emulators available to software developers before the hardware implementation is ready.
Often the details of the implementation have a strong influence on the particular instructions selected for the instruction set. For example, many implementations of the
The demands of high-speed digital signal processing have pushed in the opposite direction—forcing instructions to be implemented in a particular way. For example, to perform digital filters fast enough, the MAC instruction in a typical
See also
- Comparison of instruction set architectures
- Compressed instruction set
- Computer architecture
- Emulator
- Instruction set simulator
- Micro-operation
- No instruction set computing
- OVPsim full systems simulator providing ability to create/model/emulate any instruction set using C and standard APIs
- Processor design
- Simulation
- Register transfer language (RTL)
References
- ^ "GLOSSARY: Instruction Set Architecture (ISA)". arm.com. Archived from the original on 2023-11-11. Retrieved 2024-02-03.
- ISBN 0-262-16123-0.
- ^ Crystal Chen; Greg Novick; Kirk Shimano (December 16, 2006). "RISC Architecture: RISC vs. CISC". cs.stanford.edu. Retrieved February 21, 2015.
- doi:10.1109/2.820037.
- ^ Shaout, Adnan; Eldos, Taisir (Summer 2003). "On the Classification of Computer Architecture". International Journal of Science and Technology. 14: 3. Retrieved March 2, 2023.
- ISBN 978-1-4615-0237-1.
- ^ a b Hennessy & Patterson 2003, p. 108.
- ^ Durand, Paul. "Instruction Set Architecture (ISA)". Introduction to Computer Science CS 0.
- ^ Hennessy & Patterson 2003, p. 92.
- ^ a b Hennessy & Patterson 2003, p. 93.
- ^ a b c Cocke, John; Markstein, Victoria (January 1990). "The evolution of RISC technology at IBM" (PDF). IBM Journal of Research and Development. 34 (1): 4–11. . Retrieved 2022-10-05.
- ISBN 978-1-84882-255-9.
- ^ Venkat, Ashish; Tullsen, Dean M. (2014). Harnessing ISA Diversity: Design of a Heterogeneous-ISA Chip Multiprocessor. 41st Annual International Symposium on Computer Architecture.
- ^ "Intel® 64 and IA-32 Architectures Software Developer's Manual". Intel Corporation. Retrieved 5 October 2022.
- .
- ^ "RISC vs. CISC". cs.stanford.edu. Retrieved 2021-12-18.
- ^ Hennessy & Patterson 2003, p. 120.
- ^ Ganssle, Jack (February 26, 2001). "Proactive Debugging". embedded.com.
- ^ "Great Microprocessors of the Past and Present (V 13.4.0)". cpushack.net. Retrieved 2014-07-25.
Further reading
- .
- ISBN 1-55860-724-2. Retrieved 2023-03-04.
External links
- Media related to Instruction set architectures at Wikimedia Commons
- Programming Textfiles: Bowen's Instruction Summary Cards
- Mark Smotherman's Historical Computer Designs Page