Integrated circuit layout
In
When using a standard process—where the interaction of the many chemical, thermal, and photographic variables is known and carefully controlled—the behaviour of the final integrated circuit depends largely on the positions and interconnections of the geometric shapes. Using a computer-aided layout tool, the layout engineer—or layout technician—places and connects all of the components that make up the chip such that they meet certain criteria—typically: performance, size, density, and manufacturability. This practice is often subdivided between two primary layout disciplines: analog and digital.
The generated layout must pass a series of checks in a process known as physical verification. The most common checks in this verification process are[1][2]
- Design rule checking (DRC),
- Layout versus schematic(LVS),
- parasitic extraction,
- antenna rule checking, and
- electrical rule checking (ERC).
When all verification is complete,
In the earlier, simpler, days of IC design, layout was done by hand using opaque tapes and films, an evolution derived from early days of printed circuit board (PCB) design -- tape-out.
Modern IC layout is done with the aid of IC layout editor software, mostly automatically using EDA tools, including place and route tools or schematic-driven layout tools. Typically this involves a library of standard cells.
The manual operation of choosing and positioning the geometric shapes is informally known as "polygon pushing".[4][5][6][7][8]
See also
- Interconnects (integrated circuits)
- Physical design (electronics)
- Printed circuit board
- Integrated circuit design
- Floorplan (microelectronics)
References
- ISBN 978-3-030-96414-6, p. 9.
- S2CID 201657819.
- ^ S2CID 215840278.
- ^ Dirk Jansen, editor. "The Electronic Design Automation Handbook". 2010. p. 39.
- ^ Dan Clein. "CMOS IC Layout: Concepts, Methodologies, and Tools". 1999 p. 60.
- ^ "Conference Record". 1987. p. 118.
- ^ Charles A. Harper; Harold C. Jones. "Active Electronic Component Handbook". 1996. p. 2
- ^ Riko Radojcic. "Managing More-than-Moore Integration Technology Development". 2018. p. 99
Further reading
- Clein, D. (2000). CMOS IC Layout. Newnes. ISBN 0-7506-7194-7
- Hastings, A. (2005). The Art of Analog Layout. Prentice Hall. ISBN 0-13-146410-8
- Lienig, J., Scheible, J. (2020). Fundamentals of Layout Design for Electronic Circuits. Springer. )
- Saint, Ch. and J. (2002). IC Layout Basics. McGraw-Hill. ISBN 0-07-138625-4