Integrated circuit layout

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Layout view of a simple CMOS operational amplifier

In

mylar media for photo imaging (erroneously believed[who?] to reference magnetic data—the photo process greatly predated magnetic media[citation needed
]).

When using a standard process—where the interaction of the many chemical, thermal, and photographic variables is known and carefully controlled—the behaviour of the final integrated circuit depends largely on the positions and interconnections of the geometric shapes. Using a computer-aided layout tool, the layout engineer—or layout technician—places and connects all of the components that make up the chip such that they meet certain criteria—typically: performance, size, density, and manufacturability. This practice is often subdivided between two primary layout disciplines: analog and digital.

The generated layout must pass a series of checks in a process known as physical verification. The most common checks in this verification process are[1][2]

When all verification is complete,

semiconductor device fabrication
.

In the earlier, simpler, days of IC design, layout was done by hand using opaque tapes and films, an evolution derived from early days of printed circuit board (PCB) design -- tape-out.

Modern IC layout is done with the aid of IC layout editor software, mostly automatically using EDA tools, including place and route tools or schematic-driven layout tools. Typically this involves a library of standard cells.

The manual operation of choosing and positioning the geometric shapes is informally known as "polygon pushing".[4][5][6][7][8]

See also

References

Further reading