MOSFET
The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET) is a type of
The basic principle of the field-effect transistor was first patented by Julius Edgar Lilienfeld in 1925.[1]
The main advantage of a MOSFET is that it requires almost no input current to control the load current, when compared to
The "metal" in the name MOSFET is sometimes a
The MOSFET is by far the most common transistor in
History
The basic principle of this kind of transistor was first patented by Julius Edgar Lilienfeld in 1925.[1]
The structure resembling the MOS transistor was proposed by Bell scientists William Shockley, John Bardeen and Walter Houser Brattain, during their investigation that led to discovery of the transistor effect. The structure failed to show the anticipated effects, due to the problem of surface state: traps on the semiconductor surface that hold electrons immobile. In 1955 Carl Frosch and L. Derick accidentally grew a layer of silicon dioxide over the silicon wafer. Further research showed that silicon dioxide could prevent dopants from diffusing into the silicon wafer. Building on this work Mohamed M. Atalla showed that silicon dioxide is very effective in solving the problem of one important class of surface states.[3]
Following this research,
The device was about 100 times slower than contemporary bipolar transistors and was initially seen as inferior. Nevertheless, Kahng pointed out several advantages of the device, notably ease of fabrication and its application in integrated circuits.[5]
Composition
Usually the
To overcome the increase in power consumption due to gate current leakage, a high-κ dielectric is used instead of silicon dioxide for the gate insulator, while polysilicon is replaced by metal gates (e.g. Intel, 2009).[6]
The gate is separated from the channel by a thin insulating layer, traditionally of silicon dioxide and later of
When a voltage is applied between the gate and body terminals, the electric field generated penetrates through the oxide and creates an inversion layer or channel at the semiconductor-insulator interface. The inversion layer provides a channel through which current can pass between source and drain terminals. Varying the voltage between the gate and body modulates the
Operation
Metal–oxide–semiconductor structure
The traditional metal–oxide–semiconductor (MOS) structure is obtained by growing a layer of silicon dioxide (SiO
2) on top of a silicon substrate, commonly by thermal oxidation and depositing a layer of metal or polycrystalline silicon (the latter is commonly used). As silicon dioxide is a dielectric material, its structure is equivalent to a planar capacitor, with one of the electrodes replaced by a semiconductor.
When a voltage is applied across a MOS structure, it modifies the distribution of charges in the semiconductor. If we consider a p-type semiconductor (with the density of acceptors, p the density of holes; p = NA in neutral bulk), a positive voltage, , from gate to body (see figure) creates a
Conventionally, the gate voltage at which the volume density of electrons in the inversion layer is the same as the volume density of holes in the body is called the threshold voltage. When the voltage between transistor gate and source (VGS) exceeds the threshold voltage (Vth), the difference is known as overdrive voltage.
This structure with p-type body is the basis of the n-type MOSFET, which requires the addition of n-type source and drain regions.
MOS capacitors and band diagrams
The MOS capacitor structure is the heart of the MOSFET. Consider a MOS capacitor where the silicon base is of p-type. If a positive voltage is applied at the gate, holes which are at the surface of the p-type substrate will be repelled by the electric field generated by the voltage applied. At first, the holes will simply be repelled and what will remain on the surface will be immobile (negative) atoms of the acceptor type, which creates a depletion region on the surface. A hole is created by an acceptor atom, e.g. Boron, which has one less electron than Silicon. Holes are not actually repelled, being non-entities; electrons are attracted by the positive field, and fill these holes. This creates a depletion region where no charge carriers exist because the electron is now fixed onto the atom and immobile.
As the voltage at the gate increases, there will be a point at which the surface above the depletion region will be converted from p-type into n-type, as electrons from the bulk area will start to get attracted by the larger electric field. This is known as inversion. The threshold voltage at which this conversion happens is one of the most important parameters in a MOSFET.
In the case of a p-type MOSFET, bulk inversion happens when the intrinsic energy level at the surface becomes smaller than the Fermi level at the surface. This can be seen on a band diagram. The Fermi level defines the type of semiconductor in discussion. If the Fermi level is equal to the Intrinsic level, the semiconductor is of intrinsic, or pure type. If the Fermi level lies closer to the conduction band (valence band) then the semiconductor type will be of n-type (p-type).
When the gate voltage is increased in a positive sense (for the given example),[clarify] this will shift the intrinsic energy level band so that it will curve downwards towards the valence band. If the Fermi level lies closer to the valence band (for p-type), there will be a point when the Intrinsic level will start to cross the Fermi level and when the voltage reaches the threshold voltage, the intrinsic level does cross the Fermi level, and that is what is known as inversion. At that point, the surface of the semiconductor is inverted from p-type into n-type.
If the Fermi level lies above the Intrinsic level, the semiconductor is of n-type, therefore at Inversion, when the Intrinsic level reaches and crosses the Fermi level (which lies closer to the valence band), the semiconductor type changes at the surface as dictated by the relative positions of the Fermi and Intrinsic energy levels.
Structure and channel formation
A MOSFET is based on the modulation of charge concentration by a MOS capacitance between a body electrode and a gate electrode located above the body and insulated from all other device regions by a gate dielectric layer. If dielectrics other than an oxide are employed, the device may be referred to as a metal-insulator-semiconductor FET (MISFET). Compared to the MOS capacitor, the MOSFET includes two additional terminals (source and drain), each connected to individual highly doped regions that are separated by the body region. These regions can be either p or n type, but they must both be of the same type, and of opposite type to the body region. The source and drain (unlike the body) are highly doped as signified by a "+" sign after the type of doping.
If the MOSFET is an n-channel or nMOS FET, then the source and drain are n+ regions and the body is a p region. If the MOSFET is a p-channel or pMOS FET, then the source and drain are p+ regions and the body is a n region. The source is so named because it is the source of the charge carriers (electrons for n-channel, holes for p-channel) that flow through the channel; similarly, the drain is where the charge carriers leave the channel.
The occupancy of the energy bands in a semiconductor is set by the position of the Fermi level relative to the semiconductor energy-band edges.
With sufficient gate voltage, the valence band edge is driven far from the Fermi level, and holes from the body are driven away from the gate.
At larger gate bias still, near the semiconductor surface the conduction band edge is brought close to the Fermi level, populating the surface with electrons in an inversion layer or n-channel at the interface between the p region and the oxide. This conducting channel extends between the source and the drain, and current is conducted through it when a voltage is applied between the two electrodes. Increasing the voltage on the gate leads to a higher electron density in the inversion layer and therefore increases the current flow between the source and drain. For gate voltages below the threshold value, the channel is lightly populated, and only a very small subthreshold leakage current can flow between the source and the drain.
When a negative gate-source voltage (positive source-gate) is applied, it creates a p-channel at the surface of the n region, analogous to the n-channel case, but with opposite polarities of charges and voltages. When a voltage less negative than the threshold value (a negative voltage for the p-channel) is applied between gate and source, the channel disappears and only a very small subthreshold current can flow between the source and the drain. The device may comprise a silicon on insulator device in which a buried oxide is formed below a thin semiconductor layer. If the channel region between the gate dielectric and the buried oxide region is very thin, the channel is referred to as an ultrathin channel region with the source and drain regions formed on either side in or above the thin semiconductor layer. Other semiconductor materials may be employed. When the source and drain regions are formed above the channel in whole or in part, they are referred to as raised source/drain regions.
Parameter | nMOSFET | pMOSFET | |
---|---|---|---|
Source/drain type | n-type | p-type | |
|
n-type | p-type | |
|
Polysilicon | n+ | p+ |
Metal | φm ~ Si conduction band | φm ~ Si valence band | |
Well type | p-type | n-type | |
Threshold voltage, Vth |
|
| |
Band-bending | Downwards | Upwards | |
Inversion layer carriers | Electrons | Holes | |
Substrate type | p-type | n-type |
Modes of operation
The operation of a MOSFET can be separated into three different modes, depending on the voltages at the terminals. In the following discussion, a simplified algebraic model is used.[9] Modern MOSFET characteristics are more complex than the algebraic model presented here.[10]
For an enhancement-mode, n-channel MOSFET, the three operational modes are:
Cutoff, subthreshold, and weak-inversion mode
When VGS < Vth:
where is gate-to-source bias and is the threshold voltage of the device.
According to the basic threshold model, the transistor is turned off, and there is no conduction between drain and source. A more accurate model considers the effect of thermal energy on the
In weak inversion where the source is tied to bulk, the current varies exponentially with as given approximately by:[11][12]
where = current at , the thermal voltage and the slope factor n is given by:
with = capacitance of the depletion layer and = capacitance of the oxide layer. This equation is generally used, but is only an adequate approximation for the source tied to the bulk. For the source not tied to the bulk, the subthreshold equation for drain current in saturation is[13][14]
In a long-channel device, there is no drain voltage dependence of the current once , but as channel length is reduced drain-induced barrier lowering introduces drain voltage dependence that depends in a complex way upon the device geometry (for example, the channel doping, the junction doping and so on). Frequently, threshold voltage Vth for this mode is defined as the gate voltage at which a selected value of current ID0 occurs, for example, ID0 = 1 μA, which may not be the same Vth-value used in the equations for the following modes.
Some micropower analog circuits are designed to take advantage of subthreshold conduction.[15][16][17] By working in the weak-inversion region, the MOSFETs in these circuits deliver the highest possible transconductance-to-current ratio, namely: , almost that of a bipolar transistor.[18]
The subthreshold
Triode mode or linear region (also known as the ohmic mode)
When VGS > Vth and VDS < VGS − Vth:
The transistor is turned on, and a channel has been created which allows current between the drain and the source. The MOSFET operates like a resistor, controlled by the gate voltage relative to both the source and drain voltages. The current from drain to source is modeled as:
where is the charge-carrier effective mobility, is the gate width, is the gate length and is the gate oxide capacitance per unit area. The transition from the exponential subthreshold region to the triode region is not as sharp as the equations suggest.[21][22][verification needed]
Saturation or active mode
When VGS > Vth and VDS ≥ (VGS – Vth):
The switch is turned on, and a channel has been created, which allows current between the drain and source. Since the drain voltage is higher than the source voltage, the electrons spread out, and conduction is not through a narrow channel but through a broader, two- or three-dimensional current distribution extending away from the interface and deeper in the substrate. The onset of this region is also known as pinch-off to indicate the lack of channel region near the drain. Although the channel does not extend the full length of the device, the electric field between the drain and the channel is very high, and conduction continues. The drain current is now weakly dependent upon drain voltage and controlled primarily by the gate-source voltage, and modeled approximately as:
The additional factor involving λ, the channel-length modulation parameter, models current dependence on drain voltage due to the Early effect, or channel length modulation. According to this equation, a key design parameter, the MOSFET transconductance is:
where the combination Vov = VGS − Vth is called the overdrive voltage,[23] and where VDSsat = VGS − Vth accounts for a small discontinuity in which would otherwise appear at the transition between the triode and saturation regions.
Another key design parameter is the MOSFET output resistance rout given by:
rout is the inverse of gDS where . ID is the expression in saturation region.
If λ is taken as zero, an infinite output resistance of the device results that leads to unrealistic circuit predictions, particularly in analog circuits.
As the channel length becomes very short, these equations become quite inaccurate. New physical effects arise. For example, carrier transport in the active mode may become limited by
Body effect
The occupancy of the energy bands in a semiconductor is set by the position of the Fermi level relative to the semiconductor energy-band edges. Application of a source-to-substrate reverse bias of the source-body pn-junction introduces a split between the Fermi levels for electrons and holes, moving the Fermi level for the channel further from the band edge, lowering the occupancy of the channel. The effect is to increase the gate voltage necessary to establish the channel, as seen in the figure. This change in channel strength by application of reverse bias is called the "body effect."
Simply put, using an nMOS example, the gate-to-body bias VGB positions the conduction-band energy levels, while the source-to-body bias VSB positions the electron Fermi level near the interface, deciding occupancy of these levels near the interface, and hence the strength of the inversion layer or channel.
The body effect upon the channel can be described using a modification of the threshold voltage, approximated by the following equation:
where VTB is the threshold voltage with substrate bias present, and VT0 is the zero-VSB value of threshold voltage, is the body effect parameter, and 2φB is the approximate potential drop between surface and bulk across the depletion layer when VSB = 0 and gate bias is sufficient to ensure that a channel is present.[26] As this equation shows, a reverse bias VSB > 0 causes an increase in threshold voltage VTB and therefore demands a larger gate voltage before the channel populates.
The body can be operated as a second gate, and is sometimes referred to as the "back gate"; the body effect is sometimes called the "back-gate effect".[27]
Circuit symbols
A variety of symbols are used for the MOSFET. The basic design is generally a line for the channel with the source and drain leaving it at right angles and then bending back at right angles into the same direction as the channel. Sometimes three line segments are used for
The bulk or body connection, if shown, is shown connected to the back of the channel with an arrow indicating pMOS or nMOS. Arrows always point from P to N, so an NMOS (N-channel in P-well or P-substrate) has the arrow pointing in (from the bulk to the channel). If the bulk is connected to the source (as is generally the case with discrete devices) it is sometimes angled to meet up with the source leaving the transistor. If the bulk is not shown (as is often the case in IC design as they are generally common bulk) an inversion symbol is sometimes used to indicate PMOS, alternatively an arrow on the source may be used in the same way as for bipolar transistors (out for nMOS, in for pMOS).
Comparison of enhancement-mode and depletion-mode MOSFET symbols, along with JFET symbols. The orientation of the symbols, (most significantly the position of source relative to drain) is such that more positive voltages appear higher on the page than less positive voltages, implying conventional current flowing "down" the page:[28][29][30]
P-channel | |||||
---|---|---|---|---|---|
N-channel | |||||
JFET | MOSFET enh. | MOSFET enh. (no bulk) | MOSFET dep. |
In schematics where G, S, D are not labeled, the detailed features of the symbol indicate which terminal is source and which is drain. For enhancement-mode and depletion-mode MOSFET symbols (in columns two and five), the source terminal is the one connected to the triangle. Additionally, in this diagram, the gate is shown as an "L" shape, whose input leg is closer to S than D, also indicating which is which. However, these symbols are often drawn with a T-shaped gate (as elsewhere on this page), so it is the triangle which must be relied upon to indicate the source terminal.
For the symbols in which the bulk, or body, terminal is shown, it is here shown internally connected to the source (i.e., the black triangles in the diagrams in columns 2 and 5). This is a typical configuration, but by no means the only important configuration. In general, the MOSFET is a four-terminal device, and in integrated circuits many of the MOSFETs share a body connection, not necessarily connected to the source terminals of all the transistors.
Applications
Digital
MOS integrated circuits
Following the development of
General Microelectronics introduced the first commercial MOS integrated circuit in 1964.[32] Additionally, the method of coupling two complementary MOSFETs (P-channel and N-channel) into one high/low switch, known as CMOS, means that digital circuits dissipate very little power except when actually switched.
The earliest microprocessors starting in 1970 were all MOS microprocessors; i.e., fabricated entirely from PMOS logic or fabricated entirely from NMOS logic. In the 1970s, MOS microprocessors were often contrasted with CMOS microprocessors and bipolar bit-slice processors.[33]
CMOS circuits
The MOSFET is used in digital complementary metal–oxide–semiconductor (CMOS) logic,[34] which uses p- and n-channel MOSFETs as building blocks. Overheating is a major concern in integrated circuits since ever more transistors are packed into ever smaller chips. CMOS logic reduces power consumption because no current flows (ideally), and thus no power is consumed, except when the inputs to logic gates are being switched. CMOS accomplishes this current reduction by complementing every nMOSFET with a pMOSFET and connecting both gates and both drains together. A high voltage on the gates will cause the nMOSFET to conduct and the pMOSFET not to conduct and a low voltage on the gates causes the reverse. During the switching time as the voltage goes from one state to another, both MOSFETs will conduct briefly. This arrangement greatly reduces power consumption and heat generation.
Digital
The growth of digital technologies like the
Analog
The MOSFET's advantages in digital circuits do not translate into supremacy in all
Nevertheless, MOSFETs are widely used in many types of analog circuits because of their own advantages (zero gate current, high and adjustable output impedance and improved robustness vs. BJTs which can be permanently degraded by even lightly breaking down the emitter-base).[
Some ICs combine analog and digital MOSFET circuitry on a single mixed-signal integrated circuit, making the needed board space even smaller. This creates a need to isolate the analog circuits from the digital circuits on a chip level, leading to the use of isolation rings and silicon on insulator (SOI). Since MOSFETs require more space to handle a given amount of power than a BJT, fabrication processes can incorporate BJTs and MOSFETs into a single device. Mixed-transistor devices are called bi-FETs (bipolar FETs) if they contain just one BJT-FET and BiCMOS (bipolar-CMOS) if they contain complementary BJT-FETs. Such devices have the advantages of both insulated gates and higher current density.
Analog switches
MOSFET analog switches use the MOSFET to pass analog signals when on, and as a high impedance when off. Signals flow in both directions across a MOSFET switch. In this application, the drain and source of a MOSFET exchange places depending on the relative voltages of the source and drain electrodes. The source is the more negative side for an N-MOS or the more positive side for a P-MOS. All of these switches are limited on what signals they can pass or stop by their gate-source, gate-drain and source–drain voltages; exceeding the voltage, current, or power limits will potentially damage the switch.
Single-type
This analog switch uses a four-terminal simple MOSFET of either P or N type.
In the case of an n-type switch, the body is connected to the most negative supply (usually GND) and the gate is used as the switch control. Whenever the gate voltage exceeds the source voltage by at least a threshold voltage, the MOSFET conducts. The higher the voltage, the more the MOSFET can conduct. An N-MOS switch passes all voltages less than Vgate − Vtn. When the switch is conducting, it typically operates in the linear (or ohmic) mode of operation, since the source and drain voltages will typically be nearly equal.
In the case of a P-MOS, the body is connected to the most positive voltage, and the gate is brought to a lower potential to turn the switch on. The P-MOS switch passes all voltages higher than Vgate − Vtp (threshold voltage Vtp is negative in the case of enhancement-mode P-MOS).
Dual-type (CMOS)
This "complementary" or CMOS type of switch uses one P-MOS and one N-MOS FET to counteract the limitations of the single-type switch. The FETs have their drains and sources connected in parallel, the body of the P-MOS is connected to the high potential (VDD) and the body of the N-MOS is connected to the low potential (gnd). To turn the switch on, the gate of the P-MOS is driven to the low potential and the gate of the N-MOS is driven to the high potential. For voltages between VDD − Vtn and gnd − Vtp, both FETs conduct the signal; for voltages less than gnd − Vtp, the N-MOS conducts alone; and for voltages greater than VDD − Vtn, the P-MOS conducts alone.
The voltage limits for this switch are the gate-source, gate-drain and source-drain voltage limits for both FETs. Also, the P-MOS is typically two to three times wider than the N-MOS, so the switch will be balanced for speed in the two directions.
Tri-state circuitry sometimes incorporates a CMOS MOSFET switch on its output to provide for a low-ohmic, full-range output when on, and a high-ohmic, mid-level signal when off.
Construction
Gate material
The primary criterion for the gate material is that it is a good
- The low threshold voltages(LVT) becomes a significant challenge. Additionally, obtaining low-threshold devices on both PMOS and NMOS devices sometimes requires the use of different metals for each device type.
- The silicon-SiO2 interface has been well studied and is known to have relatively few defects. By contrast many metal-insulator interfaces contain significant levels of defects which can lead to Fermi level pinning, charging, or other phenomena that ultimately degrade device performance.
- In the MOSFET IC fabricationprocess, it is preferable to deposit the gate material prior to certain high-temperature steps in order to make better-performing transistors. Such high temperature steps would melt some metals, limiting the types of metal that can be used in a metal-gate-based process.
While polysilicon gates have been the de facto standard for the last twenty years, they do have some disadvantages which have led to their likely future replacement by metal gates. These disadvantages include:
- Polysilicon is not a great conductor (approximately 1000 times more resistive than metals) which reduces the signal propagation speed through the material. The resistivity can be lowered by increasing the level of doping, but even highly doped polysilicon is not as conductive as most metals. To improve conductivity further, sometimes a high-temperature metal such as tungsten, titanium, cobalt, and more recently nickel is alloyed with the top layers of the polysilicon. Such a blended material is called silicide. The silicide-polysilicon combination has better electrical properties than polysilicon alone and still does not melt in subsequent processing. Also the threshold voltage is not significantly higher than with polysilicon alone, because the silicide material is not near the channel. The process in which silicide is formed on both the gate electrode and the source and drain regions is sometimes called salicide, self-aligned silicide.
- When the transistors are extremely scaled down, it is necessary to make the gate dielectric layer very thin, around 1 nm in state-of-the-art technologies. A phenomenon observed here is the so-called poly depletion, where a depletion layer is formed in the gate polysilicon layer next to the gate dielectric when the transistor is in the inversion. To avoid this problem, a metal gate is desired. A variety of metal gates such as tantalum, tungsten, tantalum nitride, and titanium nitride are used, usually in conjunction with high-κ dielectrics. An alternative is to use fully silicided polysilicon gates, a process known as FUSI.
Present high performance CPUs use metal gate technology, together with high-κ dielectrics, a combination known as high-κ, metal gate (HKMG). The disadvantages of metal gates are overcome by a few techniques:[36]
- The threshold voltage is tuned by including a thin "work function metal" layer between the high-κ dielectric and the main metal. This layer is thin enough that the total work function of the gate is influenced by both the main metal and thin metal work functions (either due to alloying during annealing, or simply due to the incomplete screening by the thin metal). The threshold voltage thus can be tuned by the thickness of the thin metal layer.
- High-κ dielectrics are now well studied, and their defects are understood.
- HKMG processes exist that do not require the metals to experience high temperature anneals; other processes select metals that can survive the annealing step.
Insulator
As devices are made smaller, insulating layers are made thinner, often through steps of
with Q = charge density, κ = dielectric constant, ε0 = permittivity of empty space and E = electric field. From this law it appears the same charge can be maintained in the channel at a lower field provided κ is increased. The voltage on the gate is given by:
with VG = gate voltage, Vch = voltage at channel side of insulator, and tins = insulator thickness. This equation shows the gate voltage will not increase when the insulator thickness increases, provided κ increases to keep tins / κ = constant (see the article on high-κ dielectrics for more detail, and the section in this article on gate-oxide leakage).
The insulator in a MOSFET is a dielectric which can in any event be silicon oxide, formed by LOCOS but many other dielectric materials are employed. The generic term for the dielectric is gate dielectric since the dielectric lies directly below the gate electrode and above the channel of the MOSFET.
Junction design
The source-to-body and drain-to-body
The drain induced barrier lowering of the threshold voltage and channel length modulation effects upon I-V curves are reduced by using shallow junction extensions. In addition, halo doping can be used, that is, the addition of very thin heavily doped regions of the same doping type as the body tight against the junction walls to limit the extent of depletion regions.[37]
The capacitive effects are limited by using raised source and drain geometries that make most of the contact area border thick dielectric instead of silicon.[38]
These various features of junction design are shown (with artistic license) in the figure.
Scaling
This section is written like a personal reflection, personal essay, or argumentative essay that states a Wikipedia editor's personal feelings or presents an original argument about a topic. (September 2016) |
Over the past decades, the MOSFET (as used for digital logic) has continually been scaled down in size; typical MOSFET channel lengths were once several
Smaller MOSFETs are desirable for several reasons. The main reason to make transistors smaller is to pack more and more devices in a given chip area. This results in a chip with the same functionality in a smaller area, or chips with more functionality in the same area. Since fabrication costs for a
Producing MOSFETs with channel lengths much smaller than a micrometre is a challenge, and the difficulties of semiconductor device fabrication are always a limiting factor in advancing integrated circuit technology. Though processes such as ALD have improved fabrication for small components, the small size of the MOSFET (less than a few tens of nanometers) has created operational problems:
Higher subthreshold conduction
As MOSFET geometries shrink, the voltage that can be applied to the gate must be reduced to maintain reliability. To maintain performance, the threshold voltage of the MOSFET has to be reduced as well. As threshold voltage is reduced, the transistor cannot be switched from complete turn-off to complete turn-on with the limited voltage swing available; the circuit design is a compromise between strong current in the on case and low current in the off case, and the application determines whether to favor one over the other. Subthreshold leakage (including subthreshold conduction, gate-oxide leakage and reverse-biased junction leakage), which was ignored in the past, now can consume upwards of half of the total power consumption of modern high-performance VLSI chips.[41][42]
Increased gate-oxide leakage
The gate oxide, which serves as insulator between the gate and channel, should be made as thin as possible to increase the channel conductivity and performance when the transistor is on and to reduce subthreshold leakage when the transistor is off. However, with current gate oxides with a thickness of around 1.2
Insulators that have a larger
Increased junction leakage
To make devices smaller, junction design has become more complex, leading to higher
Drain-induced barrier lowering and VT roll off
Drain-induced barrier lowering (DIBL) and VT roll off: Because of the short-channel effect, channel formation is not entirely done by the gate, but now the drain and source also affect the channel formation. As the channel length decreases, the depletion regions of the source and drain come closer together and make the threshold voltage (VT) a function of the length of the channel. This is called VT roll-off. VT also becomes function of drain to source voltage VDS. As we increase the VDS, the depletion regions increase in size, and a considerable amount of charge is depleted by the VDS. The gate voltage required to form the channel is then lowered, and thus, the VT decreases with an increase in VDS. This effect is called drain induced barrier lowering (DIBL).
Lower output resistance
For analog operation, good gain requires a high MOSFET output impedance, which is to say, the MOSFET current should vary only slightly with the applied drain-to-source voltage. As devices are made smaller, the influence of the drain competes more successfully with that of the gate due to the growing proximity of these two electrodes, increasing the sensitivity of the MOSFET current to the drain voltage. To counteract the resulting decrease in output resistance, circuits are made more complex, either by requiring more devices, for example the
Lower transconductance
The transconductance of the MOSFET decides its gain and is proportional to hole or electron mobility (depending on device type), at least for low drain voltages. As MOSFET size is reduced, the fields in the channel increase and the dopant impurity levels increase. Both changes reduce the carrier mobility, and hence the transconductance. As channel lengths are reduced without proportional reduction in drain voltage, raising the electric field in the channel, the result is velocity saturation of the carriers, limiting the current and the transconductance.
Interconnect capacitance
Traditionally, switching time was roughly proportional to the gate capacitance of gates. However, with transistors becoming smaller and more transistors being placed on the chip, interconnect capacitance (the capacitance of the metal-layer connections between different parts of the chip) is becoming a large percentage of capacitance.[46][47] Signals have to travel through the interconnect, which leads to increased delay and lower performance.
Heat production
The ever-increasing density of MOSFETs on an integrated circuit creates problems of substantial localized heat generation that can impair circuit operation. Circuits operate more slowly at high temperatures, and have reduced reliability and shorter lifetimes. Heat sinks and other cooling devices and methods are now required for many integrated circuits including microprocessors.
Process variations
With MOSFETs becoming smaller, the number of atoms in the silicon that produce many of the transistor's properties is becoming fewer, with the result that control of dopant numbers and placement is more erratic. During chip manufacturing, random process variations affect all transistor dimensions: length, width, junction depths, oxide thickness etc., and become a greater percentage of overall transistor size as the transistor shrinks. The transistor characteristics become less certain, more statistical. The random nature of manufacture means we do not know which particular example MOSFETs actually will end up in a particular instance of the circuit. This uncertainty forces a less optimal design because the design must work for a great variety of possible component MOSFETs. See
Modeling challenges
Modern ICs are computer-simulated with the goal of obtaining working circuits from the very first manufactured lot. As devices are miniaturized, the complexity of the processing makes it difficult to predict exactly what the final devices look like, and modeling of physical processes becomes more challenging as well. In addition, microscopic variations in structure due simply to the probabilistic nature of atomic processes require statistical (not just deterministic) predictions. These factors combine to make adequate simulation and "right the first time" manufacture difficult.
Other types
Dual-gate
The dual-gate MOSFET has a tetrode configuration, where both gates control the current in the device. It is commonly used for small-signal devices in radio frequency applications where biasing the drain-side gate at constant potential reduces the gain loss caused by Miller effect, replacing two separate transistors in cascode configuration. Other common uses in RF circuits include gain control and mixing (frequency conversion). The tetrode description, though accurate, does not replicate the vacuum-tube tetrode. Vacuum-tube tetrodes, using a screen grid, exhibit much lower grid-plate capacitance and much higher output impedance and voltage gains than triode vacuum tubes. These improvements are commonly an order of magnitude (10 times) or considerably more. Tetrode transistors (whether bipolar junction or field-effect) do not exhibit improvements of such a great degree.
The
Depletion-mode
There are depletion-mode MOSFET devices, which are less commonly used than the standard enhancement-mode devices already described. These are MOSFET devices that are doped so that a channel exists even with zero voltage from gate to source. To control the channel, a negative voltage is applied to the gate (for an n-channel device), depleting the channel, which reduces the current flow through the device. In essence, the depletion-mode device is equivalent to a
Due to their low
Depletion-mode MOSFET families include the BF960 by Siemens and Telefunken, and the BF980 in the 1980s by Philips (later to become NXP Semiconductors), whose derivatives are still used in AGC and RF mixer front-ends.
Metal–insulator–semiconductor field-effect transistor (MISFET)
Metal–insulator–semiconductor field-effect-transistor,[52][53][54] or MISFET, is a more general term than MOSFET and a synonym to insulated-gate field-effect transistor (IGFET). All MOSFETs are MISFETs, but not all MISFETs are MOSFETs.
The gate dielectric insulator in a MISFET is a substrate oxide (hence typically
Insulator types may be:
- Silicon dioxide, in silicon MOSFETs
- Organic insulators (e.g., undoped trans-polyacetylene; cyanoethyl pullulan, CEP[55]), for organic-based FETs.[54]
NMOS logic
For devices of equal current driving capability, n-channel MOSFETs can be made smaller than p-channel MOSFETs, due to p-channel charge carriers (
Power MOSFET
Power MOSFETs have a different structure.[56] As with most power devices, the structure is vertical and not planar. Using a vertical structure, it is possible for the transistor to sustain both high blocking voltage and high current. The voltage rating of the transistor is a function of the doping and thickness of the N-epitaxial layer (see cross section), while the current rating is a function of the channel width (the wider the channel, the higher the current). In a planar structure, the current and breakdown voltage ratings are both a function of the channel dimensions (respectively width and length of the channel), resulting in inefficient use of the "silicon estate". With the vertical structure, the component area is roughly proportional to the current it can sustain, and the component thickness (actually the N-epitaxial layer thickness) is proportional to the breakdown voltage.[57]
Power MOSFETs with lateral structure are mainly used in high-end audio amplifiers and high-power PA systems. Their advantage is a better behaviour in the saturated region (corresponding to the linear region of a bipolar transistor) than the vertical MOSFETs. Vertical MOSFETs are designed for switching applications.[58]
Double-diffused metal–oxide–semiconductor (DMOS)
There are LDMOS (lateral double-diffused metal oxide semiconductor) and VDMOS (vertical double-diffused metal oxide semiconductor). Most power MOSFETs are made using this technology.
Radiation-hardened-by-design (RHBD)
Semiconductor sub-micrometer and nanometer electronic circuits are the primary concern for operating within the normal tolerance in harsh
etc.) tolerant circuits. These special electronics are designed by applying different techniques using RHBD MOSFETs to ensure safe space journeys and safe space-walks of astronauts.See also
- Floating-gate MOSFET – Type of MOSFET where the gate is electrically isolated
- BSIM – Family of MOSFET transistor models for integrated circuit design
- ggNMOS – Electrostatic discharge (ESD) protection device
- High-electron-mobility transistor – Type of field-effect transistor
- Polysilicon depletion effect – Variation of threshold voltage in polycrystalline silicon materials
- Transistor model – Simulation of physical processes taking place in an electronic device
- Intrinsic diode – MOSFET that can handle significant power levels
References
- ^ a b Lilienfeld, Julius Edgar (1926-10-08) "Method and apparatus for controlling electric currents" U.S. patent 1745175A
- ^ "D‐MOSFET OPERATION AND BIASING" (PDF). Archived (PDF) from the original on 2022-10-22.
- Atalla, M.; Kahng, D.(1960). "Silicon-silicon dioxide field induced surface devices". IRE-AIEE Solid State Device Research Conference.
- ^ "1960 – Metal Oxide Semiconductor (MOS) Transistor Demonstrated". The Silicon Engine. Computer History Museum. Retrieved 2023-01-16.
- ^ Ross, Bassett (2002). To the Digital Age: Research Labs, Start-up Companies, and the Rise of MOS Technology. JHU Press. pp. 12–28.
- ^ "Intel 45nm Hi-k Silicon Technology". Intel. Archived from the original on July 5, 2007.
- ^ "memory components data book" (PDF). memory components data book. Intel. pp. 2–1. Archived from the original (PDF) on 4 March 2016. Retrieved 30 August 2015.
- ^ "Using a MOSFET as a Switch". 090507 brunningsoftware.co.uk
- doi:10.1109/JSSC.1968.1049902. Archived from the originalon June 10, 2013.
- ISBN 978-0-7923-8575-2. The most recent version of the BSIM model is described in V., Sriramkumar; Paydavosi, Navid; Lu, Darsen; Lin, Chung-Hsun; Dunga, Mohan; Yao, Shijing; Morshed, Tanvir; Niknejad, Ali & Hu, Chenming (2012). "BSIM-CMG 106.1.0beta Multi-Gate MOSFET Compact Model" (PDF). Department of Electronic Engineering and Computer Science, University of California Berkeley. Archived from the original(PDF) on 2014-07-27. Retrieved 2012-04-01.
- ^
Gray, P. R.; Hurst, P. J.; Lewis, S. H. & Meyer, R. G. (2001). Analysis and Design of Analog Integrated Circuits (4th ed.). New York: Wiley. pp. 66–67. ISBN 978-0-471-32168-2.
- ^
van der Meer, P. R.; van Staveren, A.; van Roermund, A. H. M. (2004). Low-Power Deep Sub-Micron CMOS Logic: Subthreshold Current Reduction. Dordrecht: Springer. p. 78. ISBN 978-1-4020-2848-9.
- ^ Degnan, Brian. "Wikipedia fails subvt".
- ISBN 9780201059922.
- ISBN 978-981-02-3377-8.
- ISBN 978-0-07-048292-0.
- ISBN 978-3-540-44108-3.
- ISBN 978-0-7803-1170-1.
- ISBN 978-1-4020-8067-8.
- ISBN 978-0-387-25738-9.
- ISBN 978-981-256-810-6.
- ISBN 978-0-02-374910-0.
- ISBN 978-0-19-514251-8.
- ISBN 978-0-471-32168-2.
- ISBN 978-0-19-514251-8.
- ^
For a uniformly doped p-type substrate with bulk acceptor doping of NA per unit volume,
ISBN 9789812707581.
- ^ "Body effect". Equars.com. Archived from the original on 2014-11-10. Retrieved 2012-06-02.
- ^ "Electronic Circuit Symbols". circuitstoday.com. 9 November 2011. Archived from the original on 13 October 2014.
- ^ IEEE Std 315-1975 — Graphic Symbols for Electrical and Electronics Diagrams (Including Reference Designation Letters)
- ^ Jaeger, Richard C.; Blalock, Travis N. "Figure 4.15 IEEE Standard MOS transistor circuit symbols". Microelectronic Circuit Design (PDF). Archived (PDF) from the original on 2022-10-09.
- ^ "1955 – Photolithography Techniques Are Used to Make Silicon Devices". Computer History Museum. Retrieved 2012-06-02.
- ^ "1964 – First Commercial MOS IC Introduced".[permanent dead link]
- ^ Cushman, Robert H. (20 September 1975). "2-1/2-generation μP's-$10 parts that perform like low-end mini's" (PDF). EDN. Archived from the original (PDF) on 24 April 2016. Retrieved 8 August 2013.
- ^ "Computer History Museum – The Silicon Engine | 1963 – Complementary MOS Circuit Configuration is Invented". Computerhistory.org. Retrieved 2012-06-02.
- ^ "Computer History Museum – Exhibits – Microprocessors". Computerhistory.org. Retrieved 2012-06-02.
- ^ "ReVera's FinFET Control". revera.com. Archived from the original on 19 September 2010.
- ISBN 978-1-4020-7018-1.
- ISBN 978-3-540-20481-7.
- ^ "International Technology Roadmap for Semiconductors". Archived from the original on 2015-12-28.
- ^ "1965 – "Moore's Law" Predicts the Future of Integrated Circuits". Computer History Museum.
- ISBN 978-0-07-143786-8.
- ISBN 978-1-59829-056-1.
- ^ "Frontier Semiconductor Paper" (PDF). Archived from the original (PDF) on February 27, 2012. Retrieved 2012-06-02.
- ISBN 978-0-8493-4199-1.
- .
- ^ "VLSI wiring capacitance" (PDF). IBM Journal of Research and Development. 9 February 2021. Archived (PDF) from the original on 2022-10-09.[dead link]
- ISBN 978-3-540-41068-3.
- ISBN 9780387309286.
- ISBN 978-981-238-222-1.
- ISBN 978-1-56677-712-4.
- ^ "Depletion Mode". Techweb. 29 January 2010. Archived from the original on 31 October 2010. Retrieved 27 November 2010.
- ^ "MIS". Semiconductor Glossary. Archived from the original on 2017-01-22. Retrieved 2017-05-14.
- ^
Hadziioannou, Georges; Malliaras, George G. (2007). Semiconducting polymers: chemistry, physics and engineering. Wiley-VCH. ISBN 978-3-527-31271-9.
- ^ a b
Jones, William (1997). Organic Molecular Solids: Properties and Applications. CRC Press. ISBN 978-0-8493-9428-7.
- ^ Xu, Wentao; Guo, Chang; Rhee, Shi-Woo (2013). "High performance organic field-effect transistors using cyanoethyl pullulan (CEP) high-k polymer cross-linked with trimethylolpropane triglycidyl ether (TTE) at low temperatures". Journal of Materials Chemistry C. 1 (25): 3955. .
- ISBN 978-0-534-94098-0.
- ^ "Power MOSFET Basics: Understanding MOSFET Characteristics Associated With The Figure of Merit". element14. Archived from the original on 5 April 2015. Retrieved 27 November 2010.
- ^ "Power MOSFET Basics: Understanding Gate Charge and Using It To Assess Switching Performance". element14. Archived from the original on 30 June 2014. Retrieved 27 November 2010.
External links
This article's use of external links may not follow Wikipedia's policies or guidelines. (September 2016) |
- How Semiconductors and Transistors Work (MOSFETs) WeCanFigureThisOut.org
- "Understanding power MOSFET data sheet parameters – Nexperia PDF Application Note AN11158" (PDF). Archived (PDF) from the original on 2022-10-09.
- "An introduction to depletion-mode MOSFETs". Archived from the original on 28 September 2008.
- "Power MOSFETs". Archived from the original on 2012-07-06. Retrieved 2010-03-04.
- "Criteria for Successful Selection of IGBT and MOSFET Modules". Archived from the original on 2012-11-12. Retrieved 2018-12-16.
- "MOSFET Process Step by Step". Archived from the original on 2009-08-22. Retrieved 2016-02-06. A Flash slide showing the fabricating process of a MOSFET in detail
- "MOSFET Calculator". Archived from the original on 2008-05-27. Retrieved 2008-06-03.
- "Advanced MOSFET issues". ecee.colorado.edu. 27 November 2010.
- "MOSFET applet".
- Nicolai, Ulrich; Reimann, Tobias; Petzoldt, Jürgen; Lutz, Josef (1998). Application Manual IGBT and MOSFET Power Modules (1st ed.). ISLE Verlag. ISBN 978-3-932633-24-9. Archived from the originalon 2 March 2012.
- Wintrich, Arendt; Nicolai, Ulrich; Tursky, Werner; Reimann, Tobias (2011). PDF-Version (PDF) (2nd ed.). Nuremberg: Semikron. ISBN 978-3-938843-66-6. Archived from the original(PDF) on 3 September 2013.
- "MIT Open Courseware 6.002 – Spring 2007".
- "MIT Open Courseware 6.012 – Fall 2009".
- "Georgia Tech BJT and FET Slides".
- "CircuitDesign: MOS Diffusion Parasitics". 14 December 2008.
- Lundstrom, Mark (2008). "Course on Physics of Nanoscale Transistors". nanoHUB Papers.
- Lundstrom, Mark (2005). "Notes on Ballistic MOSFETs". nanoHUB Papers.