Magnetic-core memory
Computer memory and Computer data storage types |
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Volatile |
Non-volatile |
Magnetic-core memory is a form of random-access computer memory. It predominated for roughly 20 years between 1955 and 1975, and is often just called core memory, or, informally, core.
Core memory uses
This writing process also causes electricity to be induced into nearby wires. If the new pulse being applied in the X-Y wires is the same as the last applied to that core, the existing field will do nothing, and no induction will result. If the new pulse is in the opposite direction, a pulse will be generated. This is normally picked up in a separate "sense" wire, allowing the system to know whether that core held a 1 or 0. As this readout process requires the core to be written, this process is known as destructive readout, and requires additional circuitry to reset the core to its original value if the process flipped it.
When not being read or written, the cores maintain the last value they had, even if the power is turned off. Therefore, they are a type of
Using smaller cores and wires, the
Although core memory is obsolete, computer memory is still sometimes called "core" even though it is made of semiconductors, particularly by people who had worked with machines having actual core memory. The files that result from saving the entire contents of memory to disk for inspection, which is nowadays commonly performed automatically when a major error occurs in a computer program, are still called "core dumps".
History
Developers
The basic concept of using the square hysteresis loop of certain magnetic materials as a storage or switching device was known from the earliest days of computer development. Much of this knowledge had developed due to an understanding of transformers, which allowed amplification and switch-like performance when built using certain materials. The stable switching behavior was well known in the electrical engineering field, and its application in computer systems was immediate. For example, J. Presper Eckert and Jeffrey Chuan Chu had done some development work on the concept in 1945 at the Moore School during the ENIAC efforts.[2]
Robotics pioneer George Devol filed a patent[3] for the first static (non-moving) magnetic memory on 3 April 1946. Devol's magnetic memory was further refined via 5 additional patents[4][5][6][7][8] and ultimately used in the first industrial robot. Frederick Viehe applied for various patents on the use of transformers for building digital logic circuits in place of relay logic beginning in 1947. A fully developed core system was patented in 1947, and later purchased by IBM in 1956.[9] This development was little-known, however, and the mainstream development of core is normally associated with three independent teams.
Substantial work in the field was carried out by the Shanghai-born American physicists An Wang and Way-Dong Woo, who created the pulse transfer controlling device in 1949.[10][11] The name referred to the way that the magnetic field of the cores could be used to control the switching of current; his patent focused on using cores to create delay-line or shift-register memory systems. Wang and Woo were working at Harvard University's Computation Laboratory at the time, and the university was not interested in promoting inventions created in their labs. Wang was able to patent the system on his own.
The MIT
In April 2011, Forrester recalled, "the Wang use of cores did not have any influence on my development of random-access memory. The Wang memory was expensive and complicated. As I recall, which may not be entirely correct, it used two cores per binary bit and was essentially a delay line that moved a bit forward. To the extent that I may have focused on it, the approach was not suitable for our purposes." He describes the invention and associated events, in 1975.[15] Forrester has since observed, "It took us about seven years to convince the industry that random-access magnetic-core memory was the solution to a missing link in computer technology. Then we spent the following seven years in the patent courts convincing them that they had not all thought of it first."[16]
A third developer involved in the early development of core was Jan A. Rajchman at RCA. A prolific inventor, Rajchman designed a unique core system using ferrite bands wrapped around thin metal tubes,[17] building his first examples using a converted aspirin press in 1949.[9] Rajchman later developed versions of the Williams tube and led development of the Selectron.[18]
Two key inventions led to the development of magnetic core memory in 1951. The first, An Wang's, was the write-after-read cycle, which solved the problem of how to use a storage medium in which the act of reading erased the data read, enabling the construction of a serial, one-dimensional shift register (of 50 bits), using two cores to store a bit. A Wang core shift register is in the Revolution exhibit at the Computer History Museum. The second, Forrester's, was the coincident-current system, which enabled a small number of wires to control a large number of cores enabling 3D memory arrays of several million bits. The first use of magnetic core was in the Whirlwind computer,[19] and Project Whirlwind's "most famous contribution was the random-access, magnetic core storage feature."[20] Commercialization followed quickly. Magnetic core was used in peripherals of the ENIAC in 1953,[21] the IBM 702[22] delivered in July 1955, and later in the 702 itself. The IBM 704 (1954) and the Ferranti Mercury (1957) used magnetic-core memory.
It was during the early 1950s that
Patent disputes
Wang's patent was not granted until 1955, and by that time magnetic-core memory was already in use. This started a long series of lawsuits, which eventually ended when
MIT wanted to charge IBM $0.02 per bit royalty on core memory. In 1964, after years of legal wrangling, IBM paid MIT $13 million for rights to Forrester's patent—the largest patent settlement to that date.[25][26]
Production economics
In 1953, tested but not-yet-strung cores cost US$0.33 each. As manufacturing volume increased, by 1970 IBM was producing 20 billion cores per year, and the price per core fell to US$0.0003. Core sizes shrank over the same period from around 0.1 inches (2.5 mm) diameter in the 1950s to 0.013 inches (0.33 mm) in 1966.[27] The power required to flip the magnetization of one core is proportional to the volume, so this represents a drop in power consumption by a factor of 125.
The cost of complete core memory systems was dominated by the cost of stringing the wires through the cores. Forrester's coincident-current system required one of the wires to be run at 45 degrees to the cores, which proved difficult to wire by machine, so that core arrays had to be assembled under microscopes by workers with fine motor control.
In 1956, a group at IBM filed for a patent on a machine to automatically thread the first few wires through each core. This machine held the full plane of cores in a "nest" and then pushed an array of hollow needles through the cores to guide the wires.[28] Use of this machine reduced the time taken to thread the straight X and Y select lines from 25 hours to 12 minutes on a 128 by 128 core array.[29]
Smaller cores made the use of hollow needles impractical, but there were numerous advances in semi-automatic core threading. Support nests with guide channels were developed. Cores were permanently bonded to a backing sheet "patch" that supported them during manufacture and later use. Threading needles were butt welded to the wires, so the needle and wire diameters were the same, and efforts were made to eliminate the use of needles.[30][31]
The most important change, from the point of view of automation, was the combination of the sense and inhibit wires, eliminating the need for a circuitous diagonal sense wire. With small changes in layout, this also allowed much tighter packing of the cores in each patch.[32][33]
By the early 1960s, the cost of core fell to the point that it became nearly universal as
Core memory was made
An example of the scale, economics, and technology of core memory in the 1960s was the 256K 36-bit word (1.2
In 1980, the price of a 16 kW (
Description
The term "core" comes from conventional transformers whose windings surround a magnetic core. In core memory, the wires pass once through any given core—they are single-turn devices. The properties of materials used for memory cores are dramatically different from those used in power transformers. The magnetic material for a core memory requires a high degree of magnetic remanence, the ability to stay highly magnetized, and a low coercivity so that less energy is required to change the magnetization direction. The core can take two states, encoding one bit. The core memory contents are retained even when the memory system is powered down (non-volatile memory). However, when the core is read, it is reset to a "zero" value. Circuits in the computer memory system then restore the information in an immediate re-write cycle.
How core memory works
The most common form of core memory, X/Y line coincident-current, used for the main memory of a computer, consists of a large number of small
Core relies on the square hysteresis loop properties of the ferrite material used to make the toroids. An electric current in a wire that passes through a core creates a magnetic field. Only a magnetic field greater than a certain intensity ("select") can cause the core to change its magnetic polarity. To select a memory location, one of the X and one of the Y lines are driven with half the current ("half-select") required to cause this change. Only the combined magnetic field generated where the X and Y lines cross (a logical AND function) is sufficient to change the state; other cores will see only half the needed field ("half-selected"), or none at all. By driving the current through the wires in a particular direction, the resulting induced field forces the selected core's magnetic flux to circulate in one direction or the other (clockwise or counterclockwise). One direction is a stored 1, while the other is a stored 0.
The toroidal shape of a core is preferred since the magnetic path is closed, there are no magnetic poles and thus very little external flux. This allows the cores to be packed closely together without their magnetic fields interacting. The alternating 45-degree positioning used in early core arrays was necessitated by the diagonal sense wires. With the elimination of these diagonal wires, tighter packing was possible.[33]
Reading and writing
The access time plus the time to rewrite is the memory cycle time.
Reading
To read a bit of core memory, the circuitry tries to flip the bit to the polarity assigned to the 0 state, by driving the selected X and Y lines that intersect at that core.
- If the bit was already 0, the physical state of the core is unaffected.
- If the bit was previously 1, then the core changes magnetic polarity. This change, after a delay, induces a voltage pulse into the Sense line.
The detection of such a pulse means that the bit had most recently contained a 1. Absence of the pulse means that the bit had contained a 0. The delay in sensing the voltage pulse is called the access time of the core memory.
Following any such read, the bit contains a 0. This illustrates why a core memory access is called a destructive read: Any operation that reads the contents of a core erases those contents, and they must immediately be recreated.
Writing
To write a bit of core memory, the circuitry assumes there has been a read operation and the bit is in the 0 state.
- To write a 1 bit, the selected X and Y lines are driven, with current in the opposite direction as for the read operation. As with the read, the core at the intersection of the X and Y lines changes magnetic polarity.
- To write a 0 bit, two methods can be applied. The first one is the same as reading process with current in the original direction. The second has reversed logic. Write 0 bit, in other words, is to inhibit the writing of a 1 bit. The same amount of current is also sent through the Inhibit line. This reduces the net current flowing through the respective core to half the select current, inhibiting change of polarity.
Combined sense and inhibit
The Sense wire is used only during the read, and the Inhibit wire is used only during the write. For this reason, later core systems combined the two into a single wire, and used circuitry in the memory controller to switch the function of the wire.
However, when Sense wire crosses too many cores, the half select current can also induce a considerable voltage across the whole line due to the superposition of the voltage at each single core. This potential risk of "misread" limits the minimum number of Sense wires.
Increasing Sense wires also requires more decode circuitry.
Combined read and write with modify
Core memory controllers were designed so that every read was followed immediately by a write (because the read forced all bits to 0, and because the write assumed this had happened).
For example, a value in memory could be read and modified almost as quickly as it could be read and written. In the PDP-6, the AOS*
(or SOS*
) instructions incremented (or decremented) the value between the read phase and the write phase of a single memory cycle (perhaps signaling the memory controller to pause briefly in the middle of the cycle). This might be twice as fast as the process of obtaining the value with a read-write cycle, incrementing (or decrementing) the value in some processor register, and then writing the new value with another read-write cycle.
Other forms of core memory
Word line core memory was often used to provide register memory. Other names for this type are linear select and 2-D. This form of core memory typically wove three wires through each core on the plane, word read, word write, and bit sense/write. To read or clear words, the full current is applied to one or more word read lines; this clears the selected cores and any that flip induce voltage pulses in their bit sense/write lines. For read, normally only one word read line would be selected; but for clear, multiple word read lines could be selected while the bit sense/write lines ignored. To write words, the half current is applied to one or more word write lines, and half current is applied to each bit sense/write line for a bit to be set. In some designs, the word read and word write lines were combined into a single wire, resulting in a memory array with just two wires per bit. For write, multiple word write lines could be selected. This offered a performance advantage over X/Y line coincident-current in that multiple words could be cleared or written with the same value in a single cycle. A typical machine's register set usually used only one small plane of this form of core memory. Some very large memories were built with this technology, for example the Extended Core Storage (ECS) auxiliary memory in the CDC 6600, which was up to 2 million 60-bit words.
Core rope memory
Core rope memory is a read-only memory (ROM) form of core memory. In this case, the cores, which had more linear magnetic materials, were simply used as transformers; no information was actually stored magnetically within the individual cores. Each bit of the word had one core. Reading the contents of a given memory address generated a pulse of current in a wire corresponding to that address. Each address wire was threaded either through a core to signify a binary [1], or around the outside of that core, to signify a binary [0]. As expected, the cores were much larger physically than those of read-write core memory. This type of memory was exceptionally reliable. An example was the Apollo Guidance Computer used for the NASA Moon landings.
Physical characteristics
Speed
The performance of early core memories can be characterized in today's terms as being very roughly comparable to a clock rate of 1
Reliability
Core memory is
Temperature sensitivity
Another characteristic of early core was that the coercive force was very temperature-sensitive; the proper half-select current at one temperature is not the proper half-select current at another temperature. So a memory controller would include a temperature sensor (typically a thermistor) to adjust the current levels correctly for temperature changes. An example of this is the core memory used by Digital Equipment Corporation for their PDP-1 computer; this strategy continued through all of the follow-on core memory systems built by DEC for their PDP line of air-cooled computers.
Another method of handling the temperature sensitivity was to enclose the magnetic core "stack" in a temperature controlled oven. Examples of this are the heated-air core memory of the
Diagnosing
Diagnosing hardware problems in core memory required time-consuming diagnostic programs to be run. While a quick test checked if every bit could contain a one and a zero, these diagnostics tested the core memory with worst-case patterns and had to run for several hours. As most computers had just a single core-memory board, these diagnostics also moved themselves around in memory, making it possible to test every bit. An advanced test was called a "
-
ThismicroSDHCcard holds 8 billion bytes (8 GB). It rests on a section of magnetic-core memory that uses 64 cores to hold eight bytes. The microSDHC card holds over one billion times more bytes in much less physical space.
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Magnetic-core memory, 18×24 bits, with a US quarter for scale
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Magnetic-core memory close-up
-
At an angle
See also
- Bubble memory
- Core dump
- Core rope memory
- Delay-line memory
- Electronic calculators
- Ferroelectric RAM
- Magnetoresistive random-access memory
- Read-mostly memory (RMM)
- Thin-film memory
- Transfluxor
- Twistor memory
References
- ^ "Computer for Apollo". MIT Science Reporter. 1965. WGBH.
- S2CID 8564797.
- ^ US 2590091, George C. Devol & Erik B. Hansell, "Magnetic storage and sensing device", published 10 April 1956
- ^ US 2741757, George C. Devol & Erik B. Hansell, "Magnetic storage and sensing device", published 10 April 1956
- ^ US 2926844, George C. Devol, "Sensing device for magnetic record", published 1 March 1960
- ^ US 3035253, George C. Devol, "Magnetic storage devices", published 15 May 1962
- ^ US 3016465, George C. Devol & Erik B. Hansel, "Coincidence detectors", published 9 Jan 1962
- ^ US 3246219, George C. Devol & Maurice J. Dunne, "Ferroresonant devices", published 12 April 1966
- ^ ISBN 1-57356-521-0.
- ^ "Wang Interview, An Wang's Early Work in Core Memories". Datamation. US: Technical Publishing Company: 161–163. March 1976.
- ^ US 2708722, Wang, An, "Pulse Transfer Controlling Device", issued 17 May 2020.
- .
- ^ US 2736880, Forrester, Jay W., "Multicoordinate digital information storage device", issued 28 February 1956
- ^ "Whirlwind" (PDF). The Computer Museum Report. Massachusetts: The Computer Museum: 13. Winter 1983 – via Microsoft.
- S2CID 25146240.
- ^ Kleiner, Art (4 February 2009). "Jay Forrester's Shock to the System". The MIT Sloan Review. US. Retrieved 1 April 2018.
- ^ Jan A. Rajchman, Magnetic System, U.S. patent 2,792,563, granted 14 May 1957.
- ^ Hittinger, William (1992). "Jan A. Rajchman". Memorial Tributes. 5. US: National Academy of Engineering: 229.
- ISBN 0-07-027363-4.
- ISBN 0932376096.
- S2CID 17518946.
- ISBN 978-0-262-51720-1.
- ^ Clarence Schultz and George Boesen, Selectors for Automatic Phonographs, U.S. patent 2,792,563, granted Feb. 2, 1960.
- ^ "An Wang Sells Core Memory Patent to IBM". US: Computer History Museum. Retrieved 12 April 2010.
- ^ "Magnetic Core Memory". CHM Revolution. Computer History Museum. Retrieved 1 April 2018.
- ^ Pugh, Johnson & Palmer 1991, p. 182
- ^ Pugh, Johnson & Palmer 1991, pp. 204–6
- ^ Walter P. Shaw and Roderick W. Link, Method and Apparatus for Threading Perforated Articles, U.S. patent 2,958,126, granted Nov. 1, 1960.
- ISBN 0-262-52393-0.
- ^ Robert L. Judge, Wire Threading Method and Apparatus, U.S. patent 3,314,131, granted Apr. 18, 1967.
- ^ Ronald A. Beck and Dennis L. Breu, Core Patch Stringing Method, U.S. patent 3,872,581, granted Mar. 25, 1975.
- ^ a b Creighton D. Barnes, et al., Magnetic core storage device having a single winding for both the sensing and inhibit function, U.S. patent 3,329,940, granted 4 July 1967.
- ^ a b Victor L. Sell and Syed Alvi, High Density Core Memory Matrix, U.S. patent 3,711,839, granted Jan. 16, 1973.
- ^ "Project History: Magnetic Core Memory". web.mit.edu. Archived from the original on 14 July 2023. Retrieved 14 July 2023.
- S2CID 19179436
- S2CID 109575632.
- ^ Internally, the Moby Memory had 40 bits per word, but they were not exposed to the PDP-10 processor.
- ^ Project MAC. Progress Report IV. July 1966-July 1967 (PDF) (Report). Massachusetts Institute of Technology. p. 18. 681342. Archived from the original (PDF) on 8 May 2021. Retrieved 7 December 2020.
- ISBN 0262680920, based on the Jargon File, s.v. 'moby', p. 307
- ^ FABRI-TEK Mass Core 'Moby' Memory. US. 4 August 1967. 102731715. Retrieved 7 December 2020.
{{cite book}}
:|website=
ignored (help)CS1 maint: location missing publisher (link) - ^ Krakauer, Lawrence J. "Moby Memory". Retrieved 7 December 2020.
- ISBN 1449393748, p. 98
- ^ "Section 4". Control Data 6600 Training Manual. Control Data Corporation. June 1965. Document number 60147400.
- ^ "Magnetic Core Memory". US: National High Magnetic Field Laboratory: Museum of Electricity and Magnetism. Archived from the original on 10 June 2010.
External links
- "Interactive Tutorial - Magnetic Core Memory". National High Magnetic Field Laboratory. Retrieved 27 November 2023.
- Core Memory at Columbia University
- "Magnetic Cores". Digital Computer Basics (Rate Training Manual). Naval Education and Training Command. 1978. pp. 95–. NAVEDTRA 10088-B.
- Core Memory on the PDP-11
- Core memory and other early memory types accessed 15 April 2006
- Coincident Current Ferrite Core Memories Byte magazine, July 1976
- Casio AL-1000 calculator – Shows close-ups of the magnetic core memory in this desktop electronic calculator from the mid-1960s.
- Still used core memory in multiple devices in a German computer museum
- Werner, G.E.; Whalen, R.M.; Lockhart, N.F.; Flaker, R.C. (March 1967). "A 110-Nanosecond Ferrite Core Memory" (PDF). IBM Journal of Research and Development. 11 (2): 153–161. doi:10.1147/rd.112.0153. Archived from the original(PDF) on 26 February 2009.
- Background on core memory for computers