Memory controller
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A memory controller, also known as memory chip controller (MCC) or a memory controller unit (MCU), is a digital circuit that manages the flow of data going to and from a computer's
Memory controllers contain the logic necessary to read and write to
Some memory controllers, such as the one integrated into
History
Older Intel and PowerPC-based computers have memory controller chips that are separate from the main processor. Often these are integrated into the northbridge of the computer, also sometimes called a memory controller hub.
Most modern desktop or workstation microprocessors use an integrated memory controller (IMC), including microprocessors from
Prior to
Other examples of microprocessor architectures that use integrated memory controllers include
.While an integrated memory controller has the potential to increase the system's performance, such as by reducing memory latency, it locks the microprocessor to a specific type (or types) of memory, forcing a redesign in order to support newer memory technologies. When DDR2 SDRAM was introduced, AMD released new Athlon 64 CPUs. These new models, with a DDR2 controller, use a different physical socket (known as Socket AM2), so that they will only fit in motherboards designed for the new type of RAM. When the memory controller is not on-die, the same CPU may be installed on a new motherboard, with an updated northbridge.
Some microprocessors in the 1990s, such as the DEC
Some CPUs are designed to have their memory controllers as dedicated external components that are not part of the chipset. An example is IBM
Security
A few experimental memory controllers (mostly aimed at the server market where data protection is legally required) contain a second level of address translation, in addition to the first level of address translation performed by the CPU's memory management unit.[7]
Memory controllers integrated into certain
Memory Scrambling (in Cryptographic Theory) is supposed to prevent
However Memory Scrambling has only been designed to address DRAM-related electrical problems. The late 2010s Memory Scrambling Standards do not fix or prevent security issues or problems. The 2010s Memory Scrambling standards are not cryptographically secure, or necessarily open sourced or open to public revision or analysis.[10]
ASUS and Intel have their own memory scrambling standards. Currently ASUS motherboards have allowed the user to choose which memory scrambling standards to use [ASUS or Intel] or whether to turn the feature off entirely.
Variants
Double data rate memory
Double data rate (DDR) memory controllers are used to drive DDR SDRAM, where data is transferred on both rising and falling edges of the system's memory clock. DDR memory controllers are significantly more complicated when compared to single data rate controllers [citation needed], but they allow for twice the data to be transferred without increasing the memory cell's clock rate or bus width.
Multichannel memory
Multichannel memory memory controllers are memory controllers where the DRAM devices are separated on to multiple different buses to allow the memory controller(s) to access them in parallel. This increases the theoretical amount of bandwidth of the bus by a factor of the number of channels. While a channel for every DRAM cell would be the ideal solution, adding more channels is very difficult due to wire count, line capacitance, and the need for parallel access lines to have identical lengths.
Fully buffered memory
Fully buffered memory systems place a memory buffer device on every
In theory, the FB-DIMM's memory buffer device could be built to access any DRAM cells, allowing for memory cell agnostic memory controller design, but this has not been demonstrated, as the technology is in its infancy.
Flash memory controller
Many
See also
References
- ^ Comptia A+ Certification Exam Guide, Seventh Edition, by Mike Meyers, in the glossary, bottom of page 1278: "Chip that handles memory requests from the CPU."
- ISBN 9781590591307. Retrieved 6 February 2015.
- ^ "Memory Controller"
- ^ Vries, Hans de. "Chip Architect: AMD's Next Generation Micro Processor's Architecture". www.chip-architect.com. Retrieved 2018-03-17.
- ^ Torres, Gabriel (2008-08-26). "Inside Intel Nehalem Microarchitecture". Hardware Secrets. p. 2. Retrieved 7 September 2017.
- ^ Prickett Morgan, Timothy (2016-10-17). "IBM Brings DDR4 Memory To Bear On Power Systems". IT Jungle. p. 1. Retrieved 2017-09-07.
- ^ This is a security feature in that it allows the Operating System to provide better protection separate from using a bit to deny arbitrary code execution in (System and/or User) RAM memory areas. John Carter, Wilson Hsieh, Leigh Stoller, Mark Swansony, Lixin Zhang, et al. "Impulse: Building a Smarter Memory Controller".
- ^ "2nd Generation Intel Core Processor Family Desktop, Intel Pentium Processor Family Desktop, and Intel Celeron Processor Family Desktop" (PDF). June 2013. p. 23. Retrieved 2015-11-03.
- ^ "2nd Generation Intel Core Processor Family Mobile and Intel Celeron Processor Family Mobile" (PDF). September 2012. p. 24. Retrieved 2015-11-03.
- ^ Igor Skochinsky (2014-03-12). "Secret of Intel Management Engine". SlideShare. pp. 26–29. Retrieved 2014-07-13.
External links
- Infineon/Kingston (a memory vendor) Dual Channel DDR Memory Whitepaper – explains dual channel memory controllers, and how to use them
- Introduction to Memory Controller
- Intel guide on Single- and Multichannel Memory Modes
- What is a Memory Controller and How Does it Work
- What is Memory Controller?