OpenSPARC
OpenSPARC is an
IP core under the GNU General Public License
v2. The full OpenSPARC T1 system consists of 8 cores, each one capable of executing four threads concurrently, for a total of 32 threads. Each core executes instruction in order and its logic is split among 6 pipeline stages.
On December 11, 2007, Sun also made the UltraSPARC T2 processor's RTL available via the OpenSPARC project.[1] It was also released under the GNU General public license v2.[2] OpenSPARC T2 is 8 cores, 16 pipelines with 64 threads.
See also
- LEON
- S1 Core (a derived single-core implementation)
- FeiTeng an implementation designed and produced in China for supercomputing applications
- Field-programmable gate array
- RISC-V
References
- ^ "Sun Accelerates Grown of UltraSPARC CMT Eco System". Sun Microsystems. 2007-12-11. Retrieved 2008-05-23.
- ^ "OpenSPARC Frequently Asked Questions". Oracle. Archived from the original on 2012-10-17. Retrieved 2021-03-20.
External links
- OpenSPARC site
- T1 Specifications and Source code
- T2 Specifications and Source code
- SPARC: Open Source at Curlie
- Open Source Semiconductor Core Licensing, 25 Harvard Journal of Law & Technology 131 (2011) Article analyzing the law, technology and business of open source semiconductor cores
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