Row hammer

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Row hammer (also written as rowhammer) is a computer security exploit that takes advantage of an unintended and undesirable side effect in

memory rows that were not addressed in the original memory access. This circumvention of the isolation between DRAM memory cells results from the high cell density in modern DRAM, and can be triggered by specially crafted memory access patterns that rapidly activate the same memory rows numerous times.[1][2][3]

The row hammer effect has been used in some privilege escalation computer security exploits,[2][4][5][6] and network-based attacks are also theoretically possible.[7][8]

Different hardware-based techniques exist to prevent the row hammer effect from occurring, including required support in some processors and types of DRAM memory modules.[9][10]

Background

A high-level illustration of DRAM organization, which includes memory cells (blue squares), address decoders (green rectangles), and sense amplifiers (red squares)

In

binary value. Huge numbers of DRAM memory cells are packed into integrated circuits, together with some additional logic that organizes the cells for the purposes of reading, writing, and refreshing the data.[11][12]

Memory cells (blue squares in both illustrations) are further organized into

row activation), bits from all cells in the row are transferred into the sense amplifiers that form the row buffer (red squares in both illustrations), from which the exact bit is selected using the column address. Consequently, read operations are of a destructive nature because the design of DRAM requires memory cells to be rewritten after their values have been read by transferring the cell charges into the row buffer. Write operations decode the addresses in a similar way, but as a result of the design entire rows must be rewritten for the value of a single bit to be changed.[1]: 2–3 [11][12][13]

As a result of storing data bits using capacitors that have a natural discharge rate, DRAM memory cells lose their state over time and require periodic

lockstep memory) are most commonly used.[14]

Overview

Rapid row activations (yellow rows) may change the values of bits stored in victim row (purple row).[15]: 2 

Increased densities of

mitigation techniques to counteract disturbance errors, such as improving the isolation between cells and performing production testing. However, researchers proved in a 2014 analysis that commercially available DDR3 SDRAM chips manufactured in 2012 and 2013 are susceptible to disturbance errors, while using the term row hammer to name the associated side effect that led to observed bit flips.[1][3][15]

The opportunity for the row hammer effect to occur in DDR3 memory

bit patterns result in significantly higher disturbance error rates.[1][2][15][17]

A variant called double-sided hammering involves targeted activations of two DRAM rows surrounding a victim row: in the illustration provided in this section, this variant would be activating both yellow rows with the aim of inducing bit flips in the purple row, which in this case would be the victim row. Tests show that this approach may result in a significantly higher rate of disturbance errors, compared to the variant that activates only one of the victim row's neighboring DRAM rows.[4][18]: 19–20 [19]

As DRAM vendors have deployed mitigations, patterns had to become more sophisticated to bypass row hammer mitigations. More recent row hammer patterns include non-uniform, frequency-based patterns.[20] These patterns consist of many double-sided aggressors pairs where each of them is hammered with a different frequency, phase, and amplitude. Using this and synchronizing patterns with the REFRESH command, it is possible to very effectively determine "blind spots" where the mitigation is not able to provide protection anymore. Based on this idea, academics built a row hammer fuzzer named Blacksmith[21] that can bypass existing mitigations on all DDR4 devices.

Mitigation

Different methods exist for more or less successful detection, prevention, correction or mitigation of the row hammer effect. Tests show that simple

memory word.[1]: 8 [15]: 32  Furthermore, research shows that precisely targeted three-bit row hammer flips prevents ECC memory from noticing the modifications.[22][23]

A less effective solution is to introduce more frequent memory refreshing, with the

refresh intervals shorter than the usual 64 ms,[a] but this technique results in higher power consumption and increased processing overhead; some vendors provide firmware updates that implement this type of mitigation.[24] One of the more complex prevention measures performs counter-based identification of frequently accessed memory rows and proactively refreshes their neighboring rows; another method issues additional infrequent random refreshes of memory rows neighboring the accessed rows regardless of their access frequency. Research shows that these two prevention measures cause negligible performance impacts.[1]: 10–11 [25]

Since the release of

dual in-line memory modules (DIMMs) to mitigate the row hammer effect by automatically refreshing possible victim rows, with no negative impact on performance or power consumption. When used with DIMMs that are not pTRR-compliant, these Xeon processors by default fall back on performing DRAM refreshes at twice the usual frequency, which results in slightly higher memory access latency and may reduce the memory bandwidth by up to 2–4%.[9]

The

DDR4 products,[29][30] although it is not part of the DDR4 memory standard published by JEDEC.[31] Internally, TRR identifies possible victim rows, by counting the number of row activations and comparing it against predefined chip-specific maximum activate count (MAC) and maximum activate window (tMAW) values, and refreshes these rows to prevent bit flips. The MAC value is the maximum total number of row activations that may be encountered on a particular DRAM row within a time interval that is equal or shorter than the tMAW amount of time before its neighboring rows are identified as victim rows; TRR may also flag a row as a victim row if the sum of row activations for its two neighboring rows reaches the MAC limit within the tMAW time window.[26][32] Research showed that TRR mitigations deployed on DDR4 UDIMMs and LPDDR4X chips from devices produced between 2019 and 2020 are not effective in protecting against Rowhammer.[20]

Due to their necessity of huge numbers of rapidly performed DRAM row activations, row hammer exploits issue large numbers of uncached memory accesses that cause

cache misses, which can be detected by monitoring the rate of cache misses for unusual peaks using hardware performance counters.[4][33]

Version 5.0 of the

MemTest86 memory diagnostic software, released on December 3, 2013, added a row hammer test that checks whether computer RAM is susceptible to disturbance errors, but it only works if the computer boots UEFI; without UEFI, it boots an older version with no hammer test.[34]

Implications

Memory protection, as a way of preventing processes from accessing memory that has not been assigned to each of them, is one of the concepts behind most modern operating systems. By using memory protection in combination with other security-related mechanisms such as protection rings, it is possible to achieve privilege separation between processes, in which programs and computer systems in general are divided into parts limited to the specific privileges they require to perform a particular task. Using privilege separation can also reduce the extent of potential damage caused by computer security attacks by restricting their effects to specific parts of the system.[35][36]

Disturbance errors (explained in the

main memory by directly manipulating the underlying memory hardware.[2][4][18][37] In comparison, "conventional" attack vectors such as buffer overflows aim at circumventing the protection mechanisms at the software level, by exploiting various programming mistakes to achieve alterations of otherwise inaccessible main memory contents.[38]

Exploits

hammer:
  mov (X), %eax  // read from address X
  mov (Y), %ebx  // read from address Y
  clflush (X)    // flush cache for address X
  clflush (Y)    // flush cache for address Y
  mfence
  jmp hammer
A snippet of x86 assembly code that induces the row hammer effect (memory addresses X and Y must map to different DRAM rows in the same memory bank)[1]: 3 [4][18]: 13–15 

The initial research into the row hammer effect, published in June 2014, described the nature of disturbance errors and indicated the potential for constructing an attack, but did not provide any examples of a working security exploit.[1] A subsequent October 2014 research paper did not imply the existence of any security-related issues arising from the row hammer effect.[16]

On March 9, 2015,

cache line flush[39]) machine instruction, which was previously believed to be required for constructing an effective row hammer attack.[2][4][37]

The second exploit revealed by Project Zero runs as an unprivileged

virtual addresses to physical addresses, which results in the exploit gaining unrestricted memory access.[18]: 34, 36–57  Due to its nature and the inability of the x86-64 architecture to make clflush a privileged machine instruction, this exploit can hardly be mitigated on computers that do not use hardware with built-in row hammer prevention mechanisms. While testing the viability of exploits, Project Zero found that about half of the 29 tested laptops experienced disturbance errors, with some of them occurring on vulnerable laptops in less than five minutes of running row-hammer-inducing code; the tested laptops were manufactured between 2010 and 2014 and used non-ECC DDR3 memory.[2][4][37]

In July 2015, a group of security researchers published a paper that describes an

large pages; as a result, it demonstrates a very high-level exploit of a very low-level vulnerability.[41][42][43][44]

In October 2016, researchers published DRAMMER, an Android application that uses row hammer, together with other methods, to reliably gain root access on several popular smartphones.

CVE-2016-6728[46] and a mitigation was released by Google within a month. However, due to the general nature of possible implementations of the attack, an effective software patch is difficult to be reliably implemented. As of June 2018, most patch proposals made by academia and industry were either impractical to deploy or insufficient in stopping all attacks. As a mitigation, researchers proposed a lightweight defense that prevents attacks based on direct memory access (DMA) by isolating DMA buffers with guard rows.[47][48]

In May 2021, a Google research team announced a new exploit, Half-Double that takes advantage of the worsening physics of some of the newer DRAM chips.[49]

In March 2024, a group of researchers at

AMD Zen chips, and also announced the first use of rowhammer to exploit DDR5 SDRAM.[50][51]

See also
  • Memory scrambling
     – memory controller feature that turns user data written to the memory into pseudo-random patterns
  • Radiation hardening – the act of making electronic components resistant to damage or malfunctions caused by ionizing radiation
  • Single event upset
     – a change of state caused by ions or electromagnetic radiation striking a sensitive node in an electronic device
  • Soft error – a type of error involving erroneous changes to signals or data but no changes to the underlying device or circuit

Notes

  1. memory refresh interval becomes roughly seven times shorter than the default of 64 ms.[15]
    : 17, 26 

References

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External links

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