Semiconductor device fabrication
Semiconductor device fabrication |
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MOSFET scaling (process nodes) |
Future
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Semiconductor device fabrication is the process used to manufacture
The fabrication process is performed in highly specialized
A wafer often has several integrated circuits which are called dies as they are pieces diced from a single wafer. Individual dies are separated from a finished wafer in a process called die singulation, also called wafer dicing. The dies can then undergo further assembly and packaging.[4]
Within fabrication plants, the wafers are transported inside special sealed plastic boxes called FOUPs.[3] FOUPs in many fabs contain an internal nitrogen atmosphere[5][6] which helps prevent copper from oxidizing on the wafers. Copper is used in modern semiconductors for wiring.[7] The insides of the processing equipment and FOUPs is kept cleaner than the surrounding air in the cleanroom. This internal atmosphere is known as a mini-environment and helps improve yield which is the amount of working devices on a wafer. This mini environment is within an EFEM (equipment front end module)[8] which allows a machine to receive FOUPs, and introduces wafers from the FOUPs into the machine. Additionally many machines also handle wafers in clean nitrogen or vacuum environments to reduce contamination and improve process control.[3] Fabrication plants need large amounts of liquid nitrogen to maintain the atmosphere inside production machinery and FOUPs, which are constantly purged with nitrogen.[5][6] There can also be an air curtain or a mesh[9] between the FOUP and the EFEM which helps reduce the amount of humidity that enters the FOUP and improves yield.[10][11]
Companies that manufacture machines used in the industrial semiconductor fabrication process include ASML, Applied Materials, Tokyo Electron and Lam Research.
Feature size
Feature size is determined by the width of the smallest lines that can be patterned in a semiconductor fabrication process, this measurement is known as the linewidth.[12][13] Patterning often refers to photolithography which allows a device design or pattern to be defined on the device during fabrication.[14] F2 is used as a measurement of area for different parts of a semiconductor device, based on the feature size of a semiconductor manufacturing process. Many semiconductor devices are designed in sections called cells, and each cell represents a small part of the device such as a memory cell to store data. Thus F2 is used to measure the area taken up by these cells or sections.[15]
A specific semiconductor process has specific rules on the minimum size (width or CD/Critical Dimension) and spacing for features on each layer of the chip.[16] Normally a new semiconductor process has smaller minimum sizes and tighter spacing. In some cases, this allows a simple die shrink of a currently produced chip design to reduce costs, improve performance,[16] and increase transistor density (number of transistors per unit area) without the expense of a new design.
Early semiconductor processes had arbitrary names for generations (viz.,
Initially transistor gate length was smaller than that suggested by the process node name (e.g. 350 nm node); however this trend reversed in 2009.[20] Feature sizes can have no connection to the nanometers (nm) used in marketing. For example, Intel's former
History
20th century
An improved type of MOSFET technology, CMOS, was developed by Chih-Tang Sah and Frank Wanlass at Fairchild Semiconductor in 1963.[24][25] CMOS was commercialised by RCA in the late 1960s.[24] RCA commercially used CMOS for its 4000-series integrated circuits in 1968, starting with a 20 µm process before gradually scaling to a 10 µm process over the next several years.[26] Many early semiconductor device manufacturers developed and built their own equipment such as ion implanters.[27]
In 1963,
Semiconductor device manufacturing has since spread from Texas and California in the 1960s to the rest of the world, including Asia, Europe, and the Middle East.
Wafer size has grown over time, from 25 mm in 1960, to 50 mm in 1969, 100 mm in 1976, 125 mm in 1981, 150 mm in 1983 and 200 mm in 1992.[30][31]
In the era of 2 inch wafers, these were handled manually using tweezers and held manually for the time required for a given process. Tweezers were replaced by vacuum wands as they generate fewer particles[32] which can contaminate the wafers. Wafer carriers or cassettes, which can hold several wafers at once, were developed to carry several wafers between process steps, but wafers had to be individually removed from the carrier, processed and returned to the carrier, so acid-resistant carriers were developed to eliminate this time consuming process, so the entire cassette with wafers was dipped into wet etching and wet cleaning tanks. When wafer sizes increased to 100 mm, the entire cassette would often not be dipped as uniformity, the quality of the results across the wafer, became hard to control. By the time 150 mm wafers arrived, the cassettes were not dipped and were only used as wafer carriers and holders to store wafer, and robotics became prevalent for handling wafers. With 200 mm wafers manual handling of wafer cassettes becomes risky as they are heavier.[33]
In the 1970s, several companies migrated their semiconductor manufacturing technology from bipolar to CMOS technology.[34] Semiconductor manufacturing equipment has been considered costly since 1978.[35]
In 1984, KLA developed the first automatic reticle and photomask inspection tool.[36] In 1985, KLA developed an automatic inspection tool for silicon wafers, which replaced manual microscope inspection.[37]
In 1985, STmicroelectronics invented BCD, also called BCDMOS, a semiconductor manufacturing process using Bipolar, CMOS and LDMOS devices.[38] It can also be made with Bipolar, CMOS and DMOS devices.[39] Applied Materials developed the first practical multi chamber, or cluster wafer processing tool, the Precision 5000.[40]
Until the 1980s, physical vapor deposition was the primary technique used for depositing materials onto wafers, until the advent of chemical vapor deposition.[41] Equipment with diffusion pumps was replaced with those using turbomolecular pumps as the latter do not use oil which often contaminated wafers during processing in vacuum.[42]
200 mm diameter wafers were first used in 1990 for making chips. These became the standard until the introduction of 300 mm diameter wafers in 2000.[43][44] Bridge tools were used in the transition from 150 mm wafers to 200 mm wafers[45] and in the transition from 200 mm to 300 mm wafers.[46][47] The semiconductor industry has adopted larger wafers to cope with the increased demand for chips as larger wafers provide more surface area per wafer.[48] Over time, the industry shifted to 300 mm wafers which brought along the adoption of FOUPs,[49] but many products that are not advanced are still produced in 200 mm wafers such as analog ICs, RF chips, power ICs, BCDMOS and MEMS devices.[50] Some processes such as cleaning,[51] ion implantation,[52][53] etching,[54] annealing[55] and oxidation[56] started to adopt single wafer processing instead of batch wafer processing in order to improve the reproducibility of results.[57][58] A similar trend existed in MEMS manufacturing.[59] In 1998, Applied Materials introduced the Producer, a cluster tool that had chambers grouped in pairs for processing wafers, which shared common vacuum and supply lines but were otherwise isolated, which was revolutionary at the time as it offered higher productivity than other cluster tools without sacrificing quality, due to the isolated chamber design.[60][45]
21st century
The
Silicon on insulator (SOI) technology has been used in AMD's 130 nm, 90 nm, 65 nm, 45 nm and 32 nm single, dual, quad, six and eight core processors made since 2001.[64] During the transition from 200 mm to 300 mm wafers in 2001, many bridge tools were used which could process both 200 mm and 300 mm wafers.[65] At the time, 18 companies could manufacture chips in the leading edge 130nm process.[66]
In 2006, 450 mm wafers were expected to be adopted in 2012, and 675 mm wafers were expected to be used by 2021.[67]
Since 2009, "node" has become a commercial name for marketing purposes that indicates new generations of process technologies, without any relation to gate length, metal pitch or gate pitch.
In 2011, Intel demonstrated Fin field-effect transistors, where the gate surrounds the channel on three sides, allowing for increased energy efficiency and lower gate delay—and thus greater performance—over planar transistors at the 22nm node, because planar transistors which only have one surface acting as a channel, started to suffer from short channel effects.[77][78][79][80][81] A startup called SuVolta created a technology called Deeply Depleted Channel (DDC) to compete with FinFET transistors, which uses planar transistors at the 65 nm node which are very lightly doped.[82]
By 2018, a number of transistor architectures had been proposed for the eventual replacement of
As of 2019,
From 2020 to 2022, there was a
List of steps
This is a list of processing techniques that are employed numerous times throughout the construction of a modern electronic device; this list does not necessarily imply a specific order, nor that all techniques are taken during manufacture as, in practice the order and which techniques are applied, are often specific to process offerings by foundries, or specific to an integrated device manufacturer (IDM) for their own products, and a semiconductor device might not need all techniques. Equipment for carrying out these processes is made by a handful of companies. All equipment needs to be tested before a semiconductor fabrication plant is started.[104] These processes are done after integrated circuit design. A semiconductor fab operates 24/7[105] and many fabs use large amounts of water, primarily for rinsing the chips.[106]
- Wafer processing
- Wet cleans
- Cleaning by solvents such as acetone, trichloroethylene or ultrapure water sometimes while spinning the wafer
- Piranha solution
- RCA clean
- Wafer scrubbing
- Spin cleaning[107]
- Jet spray cleaning[107]
- Cryogenic aerosol[108]
- Megasonics[109]
- Immersion batch cleaning[110]
- Surface passivation
- Photolithography
- Photoresist coating (often as a liquid, on the entire wafer)
- Photoresist baking (solidification in an oven)
- Edge bead removal[111][112]
- Exposure (in a photolithography stepper, scanner or mask aligner)
- Post Exposure Baking (PEB) improves the durability of the photoresist
- Development (removal of parts of the resist by application of a liquid developer, leaving only parts of the wafer exposed for ion implantation, layer deposition, etching, etc)
- Ion implantation (in which dopants are embedded in the wafer creating regions of increased or decreased conductivity)
- Etching (microfabrication)
- Dry etching (plasma etching)
- Reactive-ion etching (RIE)
- Deep reactive-ion etching (DRIE)
- Atomic layer etching (ALE)
- Reactive-ion etching (RIE)
- Wet etching
- Dry etching (plasma etching)
- Chemical vapor deposition (CVD)
- Metal organic chemical vapor deposition(MOCVD), used in LEDs
- Atomic layer deposition (ALD)
- Physical vapor deposition (PVD)
- Sputtering
- Evaporation
- Epitaxy[103][114]
- Molecular beam epitaxy (MBE)[115]
- Ion beam deposition[116]
- Plasma ashing (for complete photoresist removal/photoresist stripping, also known as dry strip,[117] historically done with a chemical solvent called a resist stripper,[118] [119] to allow wafers to undergo another round of photolithography)
- Thermal treatments
- Rapid thermal processing (RTP), rapid thermal anneal
- Millisecond thermal processing, millisecond anneal, millisecond processing, flash lamp anneal (FLA)
- Laser anneal
- Furnace anneals
- Thermal oxidation
- Rapid thermal processing (RTP),
- Laser lift-off (for LED production[120])
- Electrochemical deposition (ECD). See Electroplating.
- Chemical-mechanical polishing (CMP)
- Wafer testing (where the electrical performance is verified using automatic test equipment, binning and/or laser trimming may also be carried out at this step)
- Wet cleans
- Die preparation
- Through-silicon via manufacture (for three-dimensional integrated circuits)
- Wafer mounting (wafer is mounted onto a metal frame using dicing tape)
- )
- Wafer bonding and stacking (for three-dimensional integrated circuits and MEMS)
- Redistribution layer manufacture (for WLCSP packages)
- Wafer bumping (for flip chip BGA (ball grid array), and WLCSP packages)
- Die cutting or wafer dicing
- IC packaging
- )
- IC bonding: Wire bonding, thermosonic bonding, flip chip or tape automated bonding (TAB)
- IC encapsulationor integrated heat spreader (IHS) installation
- Molding (using special plastic molding compound that may contain glass powder as filler to control thermal expansion)
- Baking
- Electroplating (plates the copper leads of the lead frames with tin to make soldering easier)
- Laser marking or silkscreen printing
- Trim and form (separates the lead frames from each other, and bends the lead frame's pins so that they can be mounted on a printed circuit board)
- IC testing
Additionally steps such as Wright etch may be carried out.
Prevention of contamination and defects
When feature widths were far greater than about 10 micrometres, semiconductor purity was not as big of an issue as it is today in device manufacturing. In the 1960s, workers could work on semiconductor devices in street clothing.[126] As devices become more integrated, cleanrooms must become even cleaner. Today, fabrication plants are pressurized with filtered air to remove even the smallest particles, which could come to rest on the wafers and contribute to defects. The ceilings of semiconductor cleanrooms have fan filter units (FFUs) at regular intervals to constantly replace and filter the air in the cleanroom; semiconductor capital equipment may also have their own FFUs to clean air in the equipment's EFEM which allows the equipment to receive wafers in FOUPs. The FFUs, combined with raised floors with grills, help ensure a laminar air flow, to ensure that particles are immediately brought down to the floor and do not stay suspended in the air due to turbulence. The workers in a semiconductor fabrication facility are required to wear cleanroom suits to protect the devices from contamination by humans.[127] To increase yield, FOUPs and semiconductor capital equipment may have a mini environment with ISO class 1 level of dust, and FOUPs can have an even cleaner micro environment.[11][8] FOUPs and SMIF pods isolate the wafers from the air in the cleanroom, increasing yield because they reduce the number of defects caused by dust particles. Also, fabs have as few people as possible in the cleanroom to make maintaining the cleanroom environment easier, since people, even when wearing cleanroom suits, shed large amounts of particles, especially when walking.[128][127][129]
Wafers
A typical
Processing
In semiconductor device fabrication, the various processing steps fall into four general categories: deposition, removal, patterning, and modification of electrical properties.
- Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD) among others. Deposition can be understood to include oxide layer formation, by thermal oxidation or, more specifically, LOCOS.
- Removal is any process that removes material from the wafer; examples include etch processes (either chemical-mechanical planarization(CMP).
- Patterning is the shaping or altering of deposited materials, and is generally referred to as lithography. For example, in conventional lithography, the wafer is coated with a chemical called a photoresist; then, a machine called an aligner or stepper focuses a mask image on the wafer using short-wavelength light; the exposed regions (for "positive" resist) are washed away by a developer solution. After Removal or other processing, the remaining photoresist is removed by "dry" plasma ashing/resist ashing or by "wet" resist stripper chemistry.[131] Wet etching was widely used in the 1960s and 1970s,[132][133] but it was replaced by dry etching/plasma etching starting at the 10 micron to 3 micron nodes[134][135] because wet etching makes undercuts which is etching under mask layers or resist layers with patterns.[136][137][138] Dry etching has become the dominant etching technique.[139]
- Modification of electrical properties has historically entailed rapid thermal annealing (RTA) to activate the dopants. Annealing was initially done at 500 to 700°C, but this was later increased to 900 to 1100°C. Implanters can either process a single wafer at a time or several, up to 17, mounted on a rotating disk.[27]
Modification of electrical properties now also extends to the reduction of a material's
A recipe in semiconductor manufacturing is a list of conditions under which a wafer will be processed by a particular machine in a processing step during manufacturing.[146] Process variability is a challenge in semiconductor processing, in which wafers are not processed evenly or the quality or effectiveness of processes carried out on a wafer are not even across the wafer surface.[147]
Front-end-of-line (FEOL) processing
FEOL processing refers to the formation of the
At the 90nm node, transistor channels made with strain engineering were introduced to improve drive current in PMOS transistors by introducing regions with Silicon-Germanium in the transistor. The same was done in NMOS transistors at the 20nm node[114]
In 2007, HKMG (high-k/metal gate) transistors were introduced by Intel at the 45nm node, which replaced polysilicon gates which in turn replaced metal gate tecnology in the 1970s.[151] High-k dielectric such as hafnium oxide (HFO2) replaced silicon oxynitride (SiON), in order to prevent large amounts of leakage current in the transistor while allowing for continued scaling or shrinking of the transistors. However HFO2 is not compatible with polysilicon gates which requires the use of a metal gate. Two approaches were used in production: gate-first and gate-last. Gate-first consists of depositing the high-k dielectric and then the gate metal such as Tantalum nitride whose workfunction depends on whether the transistor is NMOS or PMOS, polysilicon deposition, gate line patterning, source and drain ion implantation, dopant anneal, and silicidation of the polysilicon and the source and drain.[152][153] In DRAM memories this technology was first adopted in 2015.[154]
Gate-last consisted of first depositing the High-κ dielectric, creating dummy gates, manufacturing sources and drains by ion deposition and dopant annealing, depositing an "interlevel dielectric (ILD)" and then polishing, and removing the dummy gates to replace them with a metal whose workfunction depended on whether the transistor was NMOS or PMOS, thus creating the metal gate. A third process, full silicidation (FUSI)[155] was not pursued due to manufacturing problems.[156] Gate-first became dominant at the 22nm/20nm node.[157][158] HKMG has been extended from planar transistors for use in FinFET and nanosheet transistors.[159] Hafnium silicon oxynitride can also be used instead of Hafnium oxide.[160][161][3][162][163]
Since the 16nm/14nm node, Atomic layer etching (ALE) is increasingly used for etching as it offers higher precision than other etching methods. In production, plasma ALE is commonly used, which removes materials unidirectionally, creating structures with vertical walls. Thermal ALE can also be used to remove materials isotropically, in all directions at the same time but without the capability to create vertical walls. Plasma ALE was initially adopted for etching contacts in transistors, and since the 7nm node it is also used to create transistor structures by etching them.[113]
Gate oxide and implants
Front-end surface engineering is followed by growth of the
Back-end-of-line (BEOL) processing
Metal layers
Once the various semiconductor devices have been
BEoL has been used since 1995 at the 350nm and 250nm nodes (0.35 and 0.25 micron nodes), at the same time chemical mechanical polishing began to be employed. At the time, 2 metal layers for interconnect, also called metallization[164] was state-of-the-art.[165]
Since the 22nm node, some manufacturers have added a new process called middle-of-line (MOL) which connects the transistors to the rest of the interconnect made in the BEoL process. The MOL is often based on tungsten and has upper and lower layers: the lower layer connects the junctions of the transistors, and an upper layer which is a tungsten plug that connects the transistors to the interconnect. Intel at the 10nm node introduced contact-over-active-gate (COAG) which, instead of placing the contact for connecting the transistor close to the gate of the transistor, places it directly over the gate of the transistor to improve transistor density.[166]
Interconnect
Historically, the metal wires have been composed
More recently, as the number of interconnect levels for logic has substantially increased due to the large number of transistors that are now interconnected in a modern
In 2014, Applied Materials proposed the use of cobalt in interconnects at the 22nm node, used for encapsulating copper interconnects in cobalt to prevent electromigration, replacing tantalum nitride since it needs to be thicker than cobalt in this application.[166][173]
Wafer test
The highly serialized nature of wafer processing has increased the demand for metrology in between the various processing steps. For example, thin film metrology based on ellipsometry or reflectometry is used to tightly control the thickness of gate oxide, as well as the thickness, refractive index, and extinction coefficient of photoresist and other coatings.[174] Wafer test metrology equipment is used to verify that the wafers haven't been damaged by previous processing steps up until testing; if too many dies on one wafer have failed, the entire wafer is scrapped to avoid the costs of further processing. Virtual metrology has been used to predict wafer properties based on statistical methods without performing the physical measurement itself.[1]
Device test
Once the front-end process has been completed, the semiconductor devices or chips are subjected to a variety of electrical tests to determine if they function properly. The percent of devices on the wafer found to perform properly is referred to as the yield. Manufacturers are typically secretive about their yields,[175] but it can be as low as 30%, meaning that only 30% of the chips on the wafer work as intended. Process variation is one among many reasons for low yield. Testing is carried out to prevent faulty chips from being assembled into relatively expensive packages.
The yield is often but not necessarily related to device (die or chip) size. As an example, In December 2019, TSMC announced an average yield of ~80%, with a peak yield per wafer of >90% for their
The fab
Chips are also tested again after packaging, as the bond wires may be missing, or analog performance may be altered by the package. This is referred to as the "final test". Chips may also be imaged using x-rays.
Usually, the fab charges for testing time, with prices in the order of cents per second. Testing times vary from a few milliseconds to a couple of seconds, and the test software is optimized for reduced testing time. Multiple chip (multi-site) testing is also possible because many testers have the resources to perform most or all of the tests in parallel and on several chips at once.
Chips are often designed with "testability features" such as scan chains or a "built-in self-test" to speed testing and reduce testing costs. In certain designs that use specialized analog fab processes, wafers are also laser-trimmed during testing, in order to achieve tightly distributed resistance values as specified by the design.
Good designs try to test and statistically manage corners (extremes of silicon behavior caused by a high operating temperature combined with the extremes of fab processing steps). Most designs cope with at least 64 corners.
Device yield
Device yield or die yield is the number of working chips or dies on a wafer, given in percentage since the number of chips on a wafer (Die per wafer, DPW) can vary depending on the chips' size and the wafer's diameter. Yield degradation is a reduction in yield, which historically was mainly caused by dust particles, however since the 1990s, yield degradation is mainly caused by process variation, the process itself and by the tools used in chip manufacturing, although dust still remains a problem in many older fabs. Dust particles have an increasing effect on yield as feature sizes are shrunk with newer processes. Automation and the use of mini environments inside of production equipment, FOUPs and SMIFs have enabled a reduction in defects caused by dust particles. Device yield must be kept high to reduce the selling price of the working chips since working chips have to pay for those chips that failed, and to reduce the cost of wafer processing. Yield can also be affected by the design and operation of the fab.
Tight control over contaminants and the production process are necessary to increase yield. Contaminants may be chemical contaminants or be dust particles. "Killer defects" are those caused by dust particles that cause complete failure of the device (such as a transistor). There are also harmless defects. A particle needs to be 1/5 the size of a feature to cause a killer defect. So if a feature is 100 nm across, a particle only needs to be 20 nm across to cause a killer defect. Electrostatic electricity can also affect yield adversely. Chemical contaminants or impurities include heavy metals such as iron, copper, nickel, zinc, chromium, gold, mercury and silver, alkali metals such as sodium, potassium and lithium, and elements such as aluminum, magnesium, calcium, chlorine, sulfur, carbon, and fluorine. It is important for these elements to not remain in contact with the silicon, as they could reduce yield. Chemical mixtures may be used to remove these elements from the silicon; different mixtures are effective against different elements.
Several models are used to estimate yield. They are Murphy's model, Poisson's model, the binomial model, Moore's model and Seeds' model. There is no universal model; a model has to be chosen based on actual yield distribution (the location of defective chips) For example, Murphy's model assumes that yield loss occurs more at the edges of the wafer (non-working chips are concentrated on the edges of the wafer), Poisson's model assumes that defective dies are spread relatively evenly across the wafer, and Seeds's model assumes that defective dies are clustered together.[177]
Smaller dies cost less to produce (since more fit on a wafer, and wafers are processed and priced as a whole), and can help achieve higher yields since smaller dies have a lower chance of having a defect, due to their lower surface area on the wafer. However, smaller dies require smaller features to achieve the same functions of larger dies or surpass them, and smaller features require reduced process variation and increased purity (reduced contamination) to maintain high yields. Metrology tools are used to inspect the wafers during the production process and predict yield, so wafers predicted to have too many defects may be scrapped to save on processing costs.[175]
Die preparation
Once tested, a wafer is typically reduced in thickness in a process also known as "backlap",
Packaging
Plastic or ceramic packaging involves mounting the die, connecting the die pads to the pins on the package, and sealing the die. Tiny bondwires are used to connect the pads to the pins. In the 'old days' (1970s), wires were attached by hand, but now specialized machines perform the task. Traditionally, these wires have been composed of gold, leading to a lead frame (pronounced "leed frame") of solder-plated copper; lead is poisonous, so lead-free "lead frames" are now mandated by RoHS.
The packaged chips are retested to ensure that they were not damaged during packaging and that the die-to-pin interconnect operation was performed correctly. A laser then etches the chip's name and numbers on the package.
Hazardous materials
Many toxic materials are used in the fabrication process.[180] These include:
- poisonous elemental .
- poisonous compounds, such as arsine and phosphine in ion implantation doping, tungsten hexafluoride, used in CVD deposition of tungsten in transistor interconnects, and silane used for depositing polysilicon.[181]
- highly reactive liquids, such as hydrogen peroxide, fuming nitric acid, sulfuric acid, and hydrofluoric acid, used in etching and cleaning.
It is vital that workers not be directly exposed to these dangerous substances. The high degree of automation common in the IC fabrication industry helps to reduce the risks of exposure. Most fabrication facilities employ exhaust management systems, such as wet scrubbers, combustors, heated absorber cartridges, etc., to control the risk to workers and to the environment.
Timeline of commercial MOSFET nodes
See also
- Deathnium
- Glossary of microelectronics manufacturing terms
- List of semiconductor scale examples
- MOSFET
- Multigate device
- FinFET
- Semiconductor industry
- International Technology Roadmap for Semiconductors
- Semiconductor consolidation
- Local oxidation of silicon (LOCOS)
- List of integrated circuit manufacturers
- List of semiconductor fabrication plants
- Microfabrication
- Semiconductor Equipment and Materials International (SEMI) — the semiconductor industry trade association
- SEMI font for labels on wafers
- Etch pit density
- Passivation
- Planar process
- Transistor count
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{{cite book}}
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Further reading
- Kaeslin, Hubert (2008). Digital Integrated Circuit Design, from VLSI Architectures to CMOS Fabrication. Cambridge University Press., section 14.2.
- Wiki related to Chip Technology
- Yoshio, Nishi (2017). Handbook of Semiconductor Manufacturing Technology. CRC Press.