System on a chip

Source: Wikipedia, the free encyclopedia.

Not to be confused with Central processing unit.
Apple M1 system on a chip
A system on a chip from Broadcom in a Raspberry Pi

A system on a chip or system-on-chip (SoC

digital and also analog, mixed-signal and often radio frequency signal processing
functions (otherwise it may be considered on a discrete application processor).

Higher-performance SoCs are often paired with dedicated and physically separate memory and secondary storage (such as

package on package (PoP) configuration, or be placed close to the SoC. Additionally, SoCs may use separate wireless modems.[2]

An SoC integrates a

GPU, Wi-Fi and cellular network radio modems, and/or one or more coprocessors. Similar to how a microcontroller integrates a microprocessor with peripheral circuits and memory, an SoC can be seen as integrating a microcontroller with even more advanced peripherals. For an overview of integrating system components, see system integration
.

Compared to a multi-chip architecture, an SoC with equivalent functionality will have reduced

power consumption as well as a smaller semiconductor die area. This comes at the cost of reduced replaceability of components. By definition, SoC designs are fully or nearly fully integrated across different component modules. For these reasons, there has been a general trend towards tighter integration of components in the computer hardware industry
, in part due to the influence of SoCs and lessons learned from the mobile and embedded computing markets.

SoCs are very common in the

smartphones and tablet computers) and edge computing markets.[3][4]

Types

Microcontroller-based system on a chip

In general, there are three distinguishable types of SoCs:

Applications

SoCs can be applied to any computing task. However, they are typically used in mobile computing such as tablets, smartphones, smartwatches and netbooks as well as embedded systems and in applications where previously microcontrollers would be used.

Embedded systems

Where previously only microcontrollers could be used, SoCs are rising to prominence in the embedded systems market. Tighter system integration offers better reliability and

vector processing and ambient intelligence. Often embedded SoCs target the internet of things, multimedia, networking, telecommunications and edge computing
markets.

Mobile computing

System on a chip AMD Élan SC450 in Nokia 9000 Communicator

package on package), the SoC.[7]
Some examples of mobile computing SoCs include:

  • ARM
    • Exynos, used mainly by Samsung's Galaxy series of smartphones
  • Qualcomm:
    • list), used in many smartphones. In 2018, Snapdragon SoCs were being used as the backbone of laptop computers running Windows 10, marketed as "Always Connected PCs".[8][9]
  • MediaTek, typically based on ARM
    • Dimensity & Kompanio Series. Standalone application & tablet processors that power devices such as Amazon Echo Show

Personal computers

In 1992,

ARM
-powered computers, these were four discrete chips. The ARM7500 chip was their second-generation SoC, based on the ARM700, VIDC20 and IOMD controllers, and was widely licensed in embedded devices such as set-top-boxes, as well as later Acorn personal computers.

Tablet and laptop manufacturers have learned lessons from embedded systems and smartphone markets about reduced power consumption, better performance and reliability from tighter

modules, and LTE and other wireless network communications integrated on chip (integrated network interface controllers).[10]

Structure

An SoC consists of hardware

communications subsystem
to connect, control, direct and interface between these functional modules.

Functional components

Processor cores

An SoC must have at least one

IP cores.[11]

Memory

Further information: Computer memory

SoCs must have

has multiple processors, in this case it is distributed memory and must be sent via § Intermodule communication on-chip to be accessed by a different processor.[12] For further discussion of multi-processing memory issues, see cache coherence and memory latency
.

Interfaces

SoCs include external

FireWire, Ethernet, USART, SPI, HDMI, I²C, CSI, etc. These interfaces will differ according to the intended application. Wireless networking protocols such as Wi-Fi, Bluetooth, 6LoWPAN and near-field communication
may also be supported.

When needed, SoCs include analog interfaces including analog-to-digital and digital-to-analog converters, often for signal processing. These may be able to interface with different types of sensors or actuators, including smart transducers. They may interface with application-specific modules or shields.[nb 1] Or they may be internal to the SoC, such as if an analog sensor is built in to the SoC and its readings must be converted to digital signals for mathematical processing.

Digital signal processors

functional units
that compute those instructions.

Typical DSP instructions include

fused multiply-add, and convolutions
.

Other

As with other computer systems, SoCs require

crystal oscillators and phase-locked loops
.

SoC peripherals including counter-timers, real-time timers and power-on reset generators. SoCs also include voltage regulators and power management circuits.

Intermodule communication

SoCs comprise many

instructions back and forth. Because of this, all but the most trivial SoCs require communications subsystems. Originally, as with other microcomputer technologies, data bus architectures were used, but recently designs based on sparse intercommunication networks known as networks-on-chip (NoC) have risen to prominence and are forecast to overtake bus architectures for SoC design in the near future.[13]

Bus-based communication

Historically, a shared global computer bus typically connected the different components, also called "blocks" of the SoC.[13] A very common bus for SoC communications is ARM's royalty-free Advanced Microcontroller Bus Architecture (AMBA) standard.

throughput of the SoC. This is similar to some device drivers of peripherals on component-based multi-chip module
PC architectures.

Wire delay is not scalable due to continued

manycore systems on chip.[13]
: xiii 

Network on a chip

Main article: Network on a chip

In the late 2010s, a trend of SoCs implementing

more processor cores on SoCs has caused on-chip communication efficiency to become one of the key factors in determining the overall system performance and cost.[13]: xiii  This has led to the emergence of interconnection networks with router-based packet switching known as "networks on chip" (NoCs) to overcome the bottlenecks of bus-based networks.[13]
: xiii 

Networks-on-chip have advantages including destination- and application-specific

communication protocols like TCP and the Internet protocol suite for on-chip communication,[13] although they typically have fewer network layers. Optimal network-on-chip network architectures are an ongoing area of much research interest. NoC architectures range from traditional distributed computing network topologies such as torus, hypercube, meshes and tree networks to genetic algorithm scheduling to randomized algorithms such as random walks with branching and randomized time to live
(TTL).

Many SoC researchers consider NoC architectures to be the future of SoC design because they have been shown to efficiently meet power and throughput needs of SoC designs. Current NoC architectures are two-dimensional. 2D IC design has limited floorplanning choices as the number of cores in SoCs increase, so as three-dimensional integrated circuits (3DICs) emerge, SoC designers are looking towards building three-dimensional on-chip networks known as 3DNoCs.[13]

Design flow

Main articles: Electronics design flow, Physical design (electronics), and Platform-based design
See also: Systems design and Software design process
SoC design flow

A system on a chip consists of both the hardware, described in § Structure, and the software controlling the microcontroller, microprocessor or digital signal processor cores, peripherals and interfaces. The design flow for an SoC aims to develop this hardware and software at the same time, also known as architectural co-design. The design flow must also take into account optimizations (§ Optimization goals) and constraints.

Most SoCs are developed from pre-qualified hardware component

USB. The hardware blocks are put together using computer-aided design tools, specifically electronic design automation tools; the software modules are integrated using a software integrated development environment
.

SoCs components are also often designed in

computer engineers in a manner independent of time scales, which are typically specified in HDL.[15] Other components can remain software and be compiled and embedded onto soft-core processors included in the SoC as modules in HDL as IP cores
.

Once the architecture of the SoC has been defined, any new hardware elements are written in an abstract hardware description language termed register transfer level (RTL) which defines the circuit behavior, or synthesized into RTL from a high level language through high-level synthesis. These elements are connected together in a hardware description language to create the full SoC design. The logic specified to connect these components and convert between possibly different interfaces provided by different vendors is called glue logic.

Design verification

Further information: Functional verification and Signoff (electronic design automation)

Chips are verified for validation correctness before being sent to a

chip design life cycle, often quoted as 70%.[16][17] With the growing complexity of chips, hardware verification languages like SystemVerilog, SystemC, e, and OpenVera are being used. Bugs
found in the verification stage are reported to the designer.

Traditionally, engineers have employed simulation acceleration, emulation or prototyping on reprogrammable hardware to verify and debug hardware and software for SoC designs prior to the finalization of the design, known as tape-out. Field-programmable gate arrays (FPGAs) are favored for prototyping SoCs because FPGA prototypes are reprogrammable, allow debugging and are more flexible than application-specific integrated circuits (ASICs).[18][19]

With high capacity and fast compilation time, simulation acceleration and emulation are powerful technologies that provide wide visibility into systems. Both technologies, however, operate slowly, on the order of MHz, which may be significantly slower – up to 100 times slower – than the SoC's operating frequency. Acceleration and emulation boxes are also very large and expensive at over US$1 million.[citation needed]

FPGA prototypes, in contrast, use FPGAs directly to enable engineers to validate and test at, or close to, a system's full operating frequency with real-world stimuli. Tools such as Certus[20] are used to insert probes in the FPGA RTL that make signals available for observation. This is used to debug hardware, firmware and software interactions across multiple FPGAs with capabilities similar to a logic analyzer.

In parallel, the hardware elements are grouped and passed through a process of logic synthesis, during which performance constraints, such as operational frequency and expected signal delays, are applied. This generates an output known as a netlist describing the design as a physical circuit and its interconnections. These netlists are combined with the glue logic connecting the components to produce the schematic description of the SoC as a circuit which can be printed onto a chip. This process is known as place and route and precedes tape-out in the event that the SoCs are produced as application-specific integrated circuits (ASIC).

Optimization goals

SoCs must optimize

power use, area on die, communication, positioning for locality between modular units and other factors. Optimization is necessarily a design goal of SoCs. If optimization was not necessary, the engineers would use a multi-chip module
architecture without accounting for the area use, power consumption or performance of the system to the same extent.

Common optimization targets for SoC designs follow, with explanations of each. In general, optimizing any of these quantities may be a hard

multiple variables to optimize simultaneously, so Pareto efficient solutions are sought after in SoC design. Oftentimes the goals of optimizing some of these quantities are directly at odds, further adding complexity to design optimization of SoCs and introducing trade-offs
in system design.

For broader coverage of trade-offs and requirements analysis, see requirements engineering.

Targets

Power consumption

SoCs are optimized to minimize the

resistance
:

SoCs are frequently embedded in
multiple standards, so SoCs performing multimedia tasks must be computationally capable platform while being low power to run off a standard mobile battery.[12]
: 3 

Performance per watt

See also: Green computing

SoCs are optimized to maximize

distributed processing and ambient intelligence require a certain level of computational performance
, but power is limited in most SoC environments.

Waste heat

Main article: Heat generation in integrated circuits
See also: Thermal management in electronics and Thermal design power

SoC designs are optimized to minimize waste heat output on the chip. As with other integrated circuits, heat generated due to high power density are the bottleneck to further miniaturization of components.[21]: 1  The power densities of high speed integrated circuits, particularly microprocessors and including SoCs, have become highly uneven. Too much waste heat can damage circuits and erode reliability of the circuit over time. High temperatures and thermal stress negatively impact reliability, stress migration, decreased mean time between failures, electromigration, wire bonding, metastability and other performance degradation of the SoC over time.[21]: 2–9 

In particular, most SoCs are in a small physical area or volume and therefore the effects of waste heat are compounded because there is little room for it to diffuse out of the system. Because of high

transistor density is physically realizable from fabrication processes but would result in unacceptably high amounts of heat in the circuit's volume.[21]
: 1 

These thermal effects force SoC and other chip designers to apply conservative

process generation produces more heat output than the last. Compounding this problem, SoC architectures are usually heterogeneous, creating spatially inhomogeneous heat fluxes, which cannot be effectively mitigated by uniform passive cooling.[21]
: 1 

Throughput

SoCs are optimized to maximize computational and communications

throughput
.

Latency

SoCs are optimized to minimize latency for some or all of their functions. This can be accomplished by laying out elements with proper proximity and locality to each-other to minimize the interconnection delays and maximize the speed at which data is communicated between modules, functional units and memories. In general, optimizing to minimize latency is an NP-complete problem equivalent to the boolean satisfiability problem.

For tasks running on processor cores, latency and throughput can be improved with task scheduling. Some tasks run in application-specific hardware units, however, and even task scheduling may not be sufficient to optimize all software-based tasks to meet timing and throughput constraints.

Methodologies

Further information: Multi-objective optimization, Multiple-criteria decision analysis, and Architecture tradeoff analysis

Systems on chip are modeled with standard hardware verification and validation techniques, but additional techniques are used to model and optimize SoC design alternatives to make the system optimal with respect to multiple-criteria decision analysis on the above optimization targets.

Task scheduling

Task scheduling is an important activity in any computer system with multiple processes or threads sharing a single processor core. It is important to reduce § Latency and increase § Throughput for embedded software running on an SoC's § Processor cores. Not every important computing activity in a SoC is performed in software running on on-chip processors, but scheduling can drastically improve performance of software-based tasks and other tasks involving shared resources.

Software running on SoCs often schedules tasks according to

network scheduling and randomized scheduling
algorithms.

Pipelining

For broader coverage of this topic, see Pipeline (computing).

Hardware and software tasks are often pipelined in

GPUs (graphics pipeline) and RISC processors (evolutions of the classic RISC pipeline), but are also applied to application-specific tasks such as digital signal processing and multimedia manipulations in the context of SoCs.[12]

Probabilistic modeling

SoCs are often analyzed though

Poisson processes
.

Markov chains

SoCs are often modeled with Markov chains, both discrete time and continuous time variants. Markov chain modeling allows asymptotic analysis of the SoC's steady state distribution of power, heat, latency and other factors to allow design decisions to be optimized for the common case.

Fabrication

Further information: Semiconductor device fabrication

SoC chips are typically

metal–oxide–semiconductor (MOS) technology.[22] The netlists described above are used as the basis for the physical design (place and route
) flow to convert the designers' intent into the design of the SoC. Throughout this conversion process, the design is analyzed with static timing modeling, simulation and other tools to ensure that it meets the specified operational parameters such as frequency, power consumption and dissipation, functional integrity (as described in the register transfer level code) and electrical integrity.

When all known bugs have been rectified and these have been re-verified and all physical design checks are done, the physical design files describing each layer of the chip are sent to the foundry's mask shop where a full set of glass lithographic masks will be etched. These are sent to a wafer fabrication plant to create the SoC dice before packaging and testing.

SoCs can be fabricated by several technologies, including:

ASICs consume less power and are faster than FPGAs but cannot be reprogrammed and are expensive to manufacture. FPGA designs are more suitable for lower volume designs, but after enough units of production ASICs reduce the total cost of ownership.[23]

SoC designs consume less power and have a lower cost and higher reliability than the multi-chip systems that they replace. With fewer packages in the system, assembly costs are reduced as well.

However, like most

very-large-scale integration (VLSI) designs, the total cost[clarification needed] is higher for one large chip than for the same functionality distributed over several smaller chips, because of lower yields[clarification needed] and higher non-recurring engineering
costs.

When it is not feasible to construct an SoC for a particular application, an alternative is a

system in package (SiP) comprising a number of chips in a single package. When produced in large volumes, SoC is more cost-effective than SiP because its packaging is simpler.[24] Another reason SiP may be preferred is waste heat
may be too high in a SoC for a given purpose because functional components are too close together, and in an SiP heat will dissipate better from different functional modules since they are physically further apart.

Examples

Some examples of systems on a chip are:

Benchmarks

SoC research and development often compares many options. Benchmarks, such as COSMIC,[25] are developed to help such evaluations.

See also

Notes

  1. ^ In embedded systems, "shields" are analogous to expansion cards for PCs. They often fit over a microcontroller such as an Arduino or single-board computer such as the Raspberry Pi and function as peripherals for the device.

References

  1. ^ Shah, Agam (January 3, 2017). "7 dazzling smartphone improvements with Qualcomm's Snapdragon 835 chip". Network World.
  2. Conde Nast
    . Retrieved December 17, 2023.
  3. ^ Pete Bennett, EE Times. "The why, where and what of low-power SoC design." December 2, 2004. Retrieved July 28, 2015.
  4. ^ Nolan, Stephen M. "Power Management for Internet of Things (IoT) System on a Chip (SoC) Development". Design And Reuse. Retrieved September 25, 2018.
  5. ^ "Is a single-chip SOC processor right for your embedded project?". Embedded. Retrieved October 13, 2018.
  6. ^ "Qualcomm launches SoCs for embedded vision | Imaging and Machine Vision Europe". www.imveurope.com. Retrieved October 13, 2018.
  7. ^ "Samsung Galaxy S10 and S10e Teardown". iFixit. March 6, 2019.
  8. ^ "ARM is going after Intel with new chip roadmap through 2020". Windows Central. Retrieved October 6, 2018.
  9. ^ "Always Connected PCs, Extended Battery Life 4G LTE Laptops | Windows". www.microsoft.com. Retrieved October 6, 2018.
  10. ^ "Gigabit Class LTE, 4G LTE and 5G Cellular Modems | Qualcomm". Qualcomm. Retrieved October 13, 2018.
  11. ^
    OCLC 44267964
    .
  12. ^
    OCLC 869378184
    .
  13. ^
    OCLC 895661009
    .
  14. ^ "Best Practices for FPGA Prototyping of MATLAB and Simulink Algorithms". EEJournal. August 25, 2011. Retrieved October 8, 2018.
  15. ^ Bowyer, Bryan (February 5, 2005). "The 'why' and 'what' of algorithmic synthesis". EE Times. Retrieved October 8, 2018.
  16. ^ EE Times. "Is verification really 70 percent?." June 14, 2004. Retrieved July 28, 2015.
  17. ^ "Difference between Verification and Validation". Software Testing Class. August 26, 2013. Retrieved April 30, 2018. In interviews most of the interviewers are asking questions on "What is Difference between Verification and Validation?" Many people use verification and validation interchangeably but both have different meanings.
  18. ^ Rittman, Danny (January 5, 2006). "Nanometer prototyping" (PDF). Tayden Design. Retrieved October 7, 2018.
  19. ^ "FPGA Prototyping to Structured ASIC Production to Reduce Cost, Risk & TTM". Design And Reuse. Retrieved October 7, 2018.
  20. ^ Brian Bailey, EE Times. "Tektronix hopes to shake up ASIC prototyping." October 30, 2012. Retrieved July 28, 2015.
  21. ^
    OCLC 934678500
    .
  22. ISBN 978-1-4020-5352-8
    .
  23. ^ "FPGA vs ASIC: Differences between them and which one to use? – Numato Lab Help Center". numato.com. July 17, 2018. Retrieved October 17, 2018.
  24. ^ EE Times. "The Great Debate: SOC vs. SIP." March 21, 2005. Retrieved July 28, 2015.
  25. ^ "COSMIC". www.ece.ust.hk. Retrieved October 8, 2018.

Further reading

External links
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