Open NAND Flash Interface Working Group

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"ONFI" redirects here. For the medication under the brand name Onfi, see clobazam.
Open NAND Flash Interface Working Group
FormationMarch 2006
TypeIndustry trade group
PurposeFlash memory standardization
Websitewww.onfi.org

The Open NAND Flash Interface Working Group (ONFI or ONFi

NAND flash memory and devices that communicate with them. The formation of ONFI was announced at the Intel Developer Forum in March 2006.[2]

History

The group's goals did not include the development of a new consumer flash

time-to-market
of flash-based devices, and means they are likely to be incompatible with future models of NAND flash, unless and until their firmware is updated.

Thus, one of the main motivations for standardization of NAND flash was to make it easier to switch between NAND chips from different producers, thereby permitting faster development of NAND-based products and lower prices via increased competition among manufacturers. By 2006, NAND flash became increasingly a

MP3 players, and solid-state drives. Product designers wanted newer NAND flash chips, for example, to be as easily interchangeable as hard disks from different manufacturers.[6][7]

Historical similarities

The effort to standardize NAND flash may be compared to earlier standardization of

logic families, once the 74HCT sub-family become available (consisting of CMOS
components with TTL-compatible logic levels).

Members

The ONFI consortium included manufacturers of NAND flash memory such as

Hynix, Intel, Micron Technology, Phison, Western Digital, Sony and Spansion.[2] Samsung, the world's largest manufacturer of NAND flash, was absent in 2006.[8]
Vendors of NAND flash-based consumer electronics and computing products are also members.

Specifications

ONFI produced

specifications
for standard interface to NAND flash chips.

Version 1.0 of this specification was released on December 28, 2006, and made available at no cost from the ONFI web site. Samsung was still not a participant.[9] It specified:

  • a standard physical interface (
    packages
  • a standard mechanism for NAND chips to identify themselves and describe their capabilities (comparable to the
    SDRAM
    modules)
  • a standard command set for reading, writing, and erasing NAND flash
  • standard timing requirements for NAND flash
  • improved performance via a standard implementation of read cache and increased concurrency for NAND flash operations
  • improved data integrity by allowing optional error-correcting code (ECC) features

A verification product was announced in June 2009.[10]

Version 2.3 was published in August 2010. It included a protocol called EZ-NAND that hid ECC details.[11]

Version 3.0 was published in March 2011. It required fewer chip-enable pins enabling more efficient printed circuit board routing.[12] A standard developed jointly with the JEDEC was published in October 2012.[13][14]

Version 3.1, published in october of 2012, includes errata to the original ONFI 3.0 specification, adds LUN SET/GET Features commands, and implements additional data setup and hold values for NV-DDR2 interface.

Version 3.2, published on July 23, 2013, raised the data rate to 533 MB/s.[15]

Version 4.0, published on April 17, 2014, introduced the NV-DDR3 interface increases the maximum switching speed from 533 MB/s to 800 MB/s, providing a performance boost of up to 50% for high performance applications enabled by solid-state NAND storage components.[16]

Version 4.1, published on December 12, 2017, extends NV-DDR3 I/O speeds to 1066 MT/s and 1200MT/s.[17]  For better signaling performance, ONFI 4.1 adds Duty Cycle Correction (DCC), Read and Write Training for speeds greater than 800MT/s, support for lower pin cap devices with 37.5 Ohms default output resistance, and devices which require data burst exit and restart for long data input and output pauses.  For lower power, 2.5V Vcc support is added. ONFI 4.1 also includes errata to the ONFI 4.0 specification.

Version 4.2, published on February 12, 2020, extends NV-DDR3 I/O speeds to 1333MT/s, 1466MT/s and 1600MT/s. The BGA-252b four channel package is introduced which has a smaller footprint than the existing BGA-272b four channel package. To enable higher IOPS multi-plane operations, addressing restrictions related to multi-plane operations are relaxed.[18]

Version 5.0, Published in May 2021, ONFI5.0 extends NV-DDR3 I/O speeds up to 2400MT/s. A new NV-LPDDR4 lower power interface is introduced with speeds up to 2400MT/s. With the NV-LPDDR4 interface, an optional Data Bus Inversion (DBI) feature is defined. New smaller footprint BGA-178b, BGA-154b and BGA-146b packages are added. ONFI5.0 also includes other errata related to the ONFI4.2 specification.[19]

Block Abstracted NAND

ONFI created the Block Abstracted NAND addendum specification to simplify host controller design by relieving the host of the complexities of ECC, bad block management, and other low-level NAND management tasks. The ONFI Block Abstracted NAND revision 1.1 specification adds the high speed source synchronous interface, which provides up to a 5X improvement in bandwidth compared with the traditional asynchronous NAND interface.[20]

NAND Connector

The NAND Connector Specification was ratified in April 2008. It specifies a standardized connection for NAND modules (similar to DRAM DIMMs) for use in applications like caching and solid-state drives (SSDs) in PC platforms.

See also

References

  1. ONFI
    .org. Retrieved 2010-07-31.
  2. ^ a b "New Group Simplifies NAND Flash Integration". Press release. ONFI. May 9, 2006. Retrieved September 13, 2013.
  3. ONFI
    .org. Retrieved 2010-07-31.
  4. ^
    ONFI.org. Archived from the original
    (PDF) on 2012-02-19. Retrieved 2010-07-31.
  5. ^ a b Kamat, Arun. "Simplifying Flash Controller Design" (PDF).
    Hynix
    .
  6. ^ a b See this presentation by Amber Huffman and Michael Abraham of Micron.
  7. ^ Jim Cooke (September 25, 2006). "Simplify Your Flash-Memory Interface". Dr. Dobb's Journal. Retrieved September 13, 2013.
  8. ^ Tony Smith (May 11, 2006). "Intel primes Flash standardisation push: Industry body formed to define common interface". The Register. Retrieved September 13, 2013.
  9. ^ Tony Smith (January 22, 2007). "Vendors pledge to make Flash as easy to upgrade as RAM: Open Flash spec published". The Register. Retrieved September 13, 2013.
  10. ^ "Perfectus Announces Industry's First SystemVerilog-based OVM Tested ONFi Verification IP for ONFi 2.1 Specification". Press release. June 22, 2009. Retrieved September 13, 2013.
  11. ^ Mark LaPedus (August 16, 2010). "NAND specification adds error correction". EE Times. Retrieved September 13, 2013.
  12. ^ "ONFI specification version 3.0" (PDF). March 15, 2011. Retrieved September 13, 2013.
  13. ^ "JEDEC and the Open NAND Flash Interface Workgroup Publish NAND Flash Interface Interoperability Standard". Press release. JEDEC. November 6, 2012. Retrieved September 13, 2013.
  14. ^ "NAND Flash Interface Interoperability: JEDSD230" (PDF). October 30, 2012. Retrieved September 13, 2013.
  15. ^ "ONFI Announces Publication of 3.2 Standard, Pushes Data Transfer Speeds to 533 MB/sec". Press release. ONFI. July 23, 2013. Retrieved September 13, 2013.
  16. ^ "ONFI Announces Publication of 4.0 Standard, Enabling a New Generation I/O with Lower Power and Higher Bandwidth". Press release. ONFI. April 17, 2014.
  17. ^ "Specifications - ONFi". www.onfi.org. Retrieved 2018-09-18.
  18. ^ "Open NAND Flash Interface Specification Revision 4.2" (PDF). 2020-02-12.
  19. ^ "Open NAND Flash Interface Specification Revision 5.0" (PDF). 25 May 2021.
  20. ^ "Block Abstracted NAND specification version 1.1" (PDF). July 8, 2009. Retrieved September 13, 2013.

External links

Retrieved from "https://en.wikipedia.org/w/index.php?title=Open_NAND_Flash_Interface_Working_Group&oldid=1199598796"