File:VLSI design of a sixteen bit pipelined multiplier using three micron NMOS technology. (IA vlsidesignofsixt00simc).pdf
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Summary
VLSI design of a sixteen bit pipelined multiplier using three micron NMOS technology.
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| Author |
Simchik, Richard J. Jr. |
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| Title |
VLSI design of a sixteen bit pipelined multiplier using three micron NMOS technology. |
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| Description |
Subjects: Electrical engineering |
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| Language | en_US | |
| Publication date | 1985 | |
| Current location |
IA Collections: navalpostgraduateschoollibrary; fedlink; americana |
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| Accession number |
vlsidesignofsixt00simc |
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| Authority file | OCLC: 1158282380 | |
| Source | ||
Licensing
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This work is in the public domain in the United States because it is a work prepared by an officer or employee of the United States Government as part of that person’s official duties under the terms of Title 17, Chapter 1, Section 105 of the US Code.
Note: This only applies to original works of the Federal Government and not to the work of any individual U.S. state, territory, commonwealth, county, municipality, or any other subdivision. This template also does not apply to postage stamp designs published by the United States Postal Service since 1978. (See § 313.6(C)(1) of Compendium of U.S. Copyright Office Practices). It also does not apply to certain US coins; see The US Mint Terms of Use.
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| This file has been identified as being free of known restrictions under copyright law, including all related and neighboring rights. | ||
File history
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| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 02:31, 2 July 2020 |  | 1,179 × 1,566, 106 pages (5.38 MB) | Fæ | FEDLINK - United States Federal Collection vlsidesignofsixt00simc (User talk:Fæ/CCE volumes#Fork8) (batch 1983-1986 #8480) |
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