Floorplan (microelectronics)

In

In modern electronic design process floorplans are created during the floorplanning design stage, an early stage in the hierarchical approach to integrated circuit design.

Depending on the design methodology being followed, the actual definition of a floorplan may differ.

Floorplanning

Floorplanning takes in some of the geometrical constraints in a design. Here are some examples:

• bonding pads for off-chip connections (often using wire bonding
  ) are normally located at the circumference of the chip;
• line drivers often have to be located as close to bonding pads as possible;
• chip area is therefore in some cases given a minimum area in order to fit in the required number of pads;
• areas are clustered in order to limit data paths thus frequently featuring defined structures such as cache RAM, multiplier, barrel shifter, line driver and arithmetic logic unit;
• purchased intellectual property blocks (
  processor core
  , come in predefined area blocks;
• some IP-blocks come with legal limitations such as permitting no routing of signals directly above the block.

Mathematical models and optimization problems

In some approaches the floorplan may be a partition of the whole chip area into

A sliceable floorplan is a floorplan that may be defined recursively as described below. ^[1]

• A floorplan that consists of a single rectangular block is sliceable.
• If a block from a sliceable floorplan is cut ("sliced") in two by a vertical or horizontal line, the resulting floorplan is sliceable.

Sliceable floorplans have been used in a number of early

• The Chip Planner of the PLAYOUT System
• VLSI Physical Design: From Graph Partitioning to Timing Closure, by Kahng, Lienig, Markov and Hu,
  ISBN 978-3-030-96414-6
  , 2022
• Fundamentals of Layout Design for Electronic Circuits, by Lienig, Scheible, Springer,
  ISBN 978-3-030-39284-0
  , 2020