Frequency divider
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A frequency divider, also called a clock divider or scaler or prescaler, is a circuit that takes an input signal of a frequency, , and generates an output signal of a frequency:
where is an integer.
Analog
Analog frequency dividers are less common and used only at very high frequencies. Digital dividers implemented in modern IC technologies can work up to tens of GHz.[citation needed]
Regenerative
A regenerative frequency divider, also known as a Miller frequency divider,[1] mixes the input signal with the feedback signal from the mixer.
The feedback signal is . This produces sum and difference frequencies , at the output of the mixer. A low pass filter removes the higher frequency, and the frequency is amplified and fed back into the mixer.
Injection-locked
A free-running
It operates similarly to an
Digital
For power-of-2 integer division, a simple binary counter can be used, clocked by the input signal. The least-significant output bit alternates at 1/2 the rate of the input clock, the next bit at 1/4 the rate, the third bit at 1/8 the rate, etc. An arrangement of flipflops is a classic method for integer-n division. Such division is frequency and phase coherent to the source over environmental variations, including temperature. The easiest configuration is a series where each flip-flop is a divide-by-2. For a series of three of these, such a system would be a divide-by-8. By adding additional logic gates to the chain of flip-flops, other division ratios can be obtained. Integrated circuit logic families can provide a single-chip solution for some common division ratios.
Another popular circuit to divide a digital signal by an even integer multiple is a
Mixed signal
(Classification: asynchronous sequential logic)
An arrangement of
Fractional-N synthesis
A fractional-n frequency synthesizer can be constructed using two integer dividers, a divide-by-N, and a divide-by-(N + 1) frequency divider. With a modulus controller, N is toggled between the two values so that the VCO alternates between one locked frequency and the other. The VCO stabilizes at a frequency that is the time average of the two locked frequencies. By varying the percentage of time the frequency divider spends at the two divider values, the frequency of the locked VCO can be selected with very fine granularity.
Delta-sigma
If the sequence of divide by N and divide by (N + 1) is periodic, spurious signals appear at the VCO output in addition to the desired frequency. Delta-sigma fractional-n dividers overcome this problem by randomizing the selection of N and (N + 1) while maintaining the time-averaged ratios.
See also
References
External links
- Digital frequency dividers
- Divide by 2, and asynchronous 2N Ripple Counter dividers - Electronics Tutorials
- Synchronous divide by 3, 6, 9, 12 with 50% duty cycle output - ON Semiconductor
- Synchronous divide by 3 or 5 with 50% duty cycle output, and divide by 1.5 & 2.5 circuits - Xilinx
- Divide by N-0.5 using 74x161 counters - Whitepaper