Memory timings
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Memory timings or RAM timings describe the timing information of a memory module or the onboard LPDDRx. Due to the inherent qualities of
The timing of modern
What determines absolute latency (and thus system performance) is determined by both the timings and the memory clock frequency. When translating memory timings into actual latency, it is important to note that timings are in units of clock cycles, which for double data rate memory is half the speed of the commonly quoted transfer rate. Without knowing the clock frequency it is impossible to state if one set of timings is "faster" than another.
For example, DDR3-2000 memory has a 1000 MHz clock frequency, which yields a 1 ns clock cycle. With this 1 ns clock, a CAS latency of 7 gives an absolute CAS latency of 7 ns. Faster DDR3-2666 memory (with a 1333 MHz clock, or 0.75 ns per cycle) may have a larger CAS latency of 9, but at a clock frequency of 1333 MHz the amount of time to wait 9 clock cycles is only 6.75 ns. It is for this reason that DDR3-2666 CL9 has a smaller absolute CAS latency than DDR3-2000 CL7 memory.
Both for DDR3 and DDR4, the four timings described earlier are not the only relevant timings and give a very short overview of the performance of memory. The full memory timings of a memory module are stored inside of a module's SPD chip. On
Modern
Note:
Increasing memory bandwidth, even while increasing memory latency, may improve the performance of a computer system with multiple processors and/or multiple execution threads. Higher bandwidth will also boost performance of integrated graphics processors that have no dedicated
Name | Symbol | Definition |
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CAS latency | CL | The number of cycles between sending a column address to the memory and the beginning of the data in response. This is the number of cycles it takes to read the first bit of memory from a DRAM with the correct row already open. Unlike the other numbers, this is not a minimum, but an exact number that must be agreed on between the memory controller and the memory. |
Row Address to Column Address Delay | TRCD | The minimum number of clock cycles required between opening a row of memory and accessing columns within it. The time to read the first bit of memory from a DRAM without an active row is TRCD + CL. |
Row Precharge Time | TRP | The minimum number of clock cycles required between issuing the precharge command and opening the next row. The time to read the first bit of memory from a DRAM with the wrong row open is TRP + TRCD + CL. |
Row Active Time | TRAS | The minimum number of clock cycles required between a row active command and issuing the precharge command. This is the time needed to internally refresh the row, and overlaps with TRCD. In SDRAM modules, it is simply TRCD + CL. Otherwise, approximately equal to TRCD + 2×CL. |
Notes:
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Handling in BIOS
In Intel systems, memory timings and management are handled by the
See also
- Serial Presence Detect
- JEDEC
- Eye pattern
- Overshoot and crosstalk
References
- ^ Posted by Alex Watson, possibly repost from original content on custompc.com [unclear] (2007-11-27). "The life and times of the modern motherboard". p. 8. Archived from the original on 22 July 2012. Retrieved 23 December 2016.
- ^ Pelner, Jenny; Pelner, James. "Minimal Intel Architecture Boot Loader (323246)" (PDF). Intel. Retrieved 12 November 2022.