Ricoh 5A22
 | This article needs additional citations for verification. (November 2011) |
 Ricoh 5A22-02 | |
| General information | |
|---|---|
| Designed by | Ricoh |
| Performance | |
| Max. CPU clock rate | 1.79 MHz to 3.58 MHz |
| Data width | 8-bit |
| Address width | 24-bit |
The Ricoh 5A22 is an 8/16-bit
address bus. The CPU runs between 1.79 MHz and 3.58 MHz, and uses an extended MOS Technology 6502 instruction set
.
Major features
In addition to the 65C816 CPU core, the 5A22 contains support hardware, including:
- Controller port interface circuits, including serialaccess to controller data
- An 8-bit parallel I/O port, which is mostly unused in the SNES
- Circuitry for generating non-maskable interrupts on V-blank
- Circuitry for generating interrupts on calculated screen positions
- A DMA unit, supporting two primary modes:
- General DMA, for block transfers at a rate of 2.68 MB/s
- scanline outside of the active display period
- Multiplication and division registers
- Two separate registers
Performance
The CPU as a whole employs a variable-speed system bus, with bus access times determined by the memory location accessed. The bus runs at 3.58 MHz for non-access cycles and when accessing Bus B and most internal registers, and either 2.68 or 3.58 MHz when accessing Bus A. It runs at 1.79 MHz only when accessing the controller port serial-access registers.[1] It works at approximately 1.5 MIPS, and has a theoretical peak performance of 1.79 million 16-bit operations per second.
See also
- Super Nintendo Entertainment System technical specifications
- Nintendo SA-1, a co-processor for the SNES based on the same 65C816 CPU core
References
- ^ anomie (December 21, 2008). "Anomie's SNES Memory Mapping Doc" (text). Retrieved April 24, 2022.