OpenRISC 1200
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A synthesizable CPU core, it was for many years maintained by developers at OpenCores.org, although, since 2015, that activity has now been taken over by the Free and Open Source Silicon Foundation at the librecores.org website. The Verilog RTL description is released under the GNU Lesser General Public License (LGPL).
Architecture
The
CPU/DSP
The OR1200 CPU is an implementation of the 32-bit ORBIS32
Memory management
The OR1200 design uses a
Performance
The core achieves 1.34
Under the worst case, the clock frequency for the OR1200 is 250 MHz at a 0.18 μm 6LM fabrication process. Using the Dhrystone benchmark, a 250 MHz OR1200 processor performs 250 Dhrystone millions of instructions per second (DMIPS) in the worst case. Estimated power usage of a 250 MHz processor at a 0.18 μm process is less than 1 W at full throttle and less than 5 mW at half throttle.[citation needed]
Applications
Generally, the OR1200 is intended to be used in a variety of embedded applications, including telecommunications, portable media, home entertainment, and automotive applications. The GNU toolchain (including GCC) has also been successfully ported to the architecture, although it is not bug-free.[3] There is a port of the Linux kernel for OR1K which runs on the OR1200. Recent ports of the embedded C libraries newlib and uClibc are also available for the platform.
Implementations
The OR1200 has been successfully implemented using FPGA and ASIC technologies.
History
The first public record of the OpenRISC 1000 architecture is in 2000.[4]
References
- ^ [1] Archived 2017-01-15 at the Wayback Machine
- ^ "OR1200 OpenRISC Processor - OR1K :: OpenCores". opencores.org. Archived from the original on 2011-09-25.
- ^ "UClibc tool chain test results - OR1K :: OpenCores". opencores.org. Archived from the original on 2012-02-22.
- ^ "Free 32-bit processor core hits the Net". 28 February 2000.
- ORSoC.se "OpenRISC 1200 development board". March 2009
- Cragie, Robert. "OpenRISC Resources Page." Asisi. March 19, 2008.