64b/66b encoding
This article includes a list of general references, but it lacks sufficient corresponding inline citations. (January 2017) |
In data networking and transmission, 64b/66b is a
The
The overhead can be reduced further by doubling the payload size to produce the 128b/130b encoding used by
Function
As its scheme name suggests, 64 payload bits are encoded as a 66-bit entity. The 66-bit entity is made by prefixing one of two possible 2-bit preambles to the 64 payload bits.
- If the preamble is 012, the 64 payload bits are data.
- If the preamble is 102, the 64 payload bits hold an 8-bit Type field and 56 bits of control information and/or data.
The preambles 002 and 112 are not used and indicate an error if seen.
The use of the 012 and 102 preambles guarantees a bit transition every 66 bits, which means that a continuous stream of 0s or 1s cannot be valid data. It also allows easier clock/timer synchronization, as a transition must be seen every 66 bits.
The 64-bit payload is then scrambled using a self-synchronous
The encoding and scrambling are normally implemented entirely in hardware, with the scrambler using a linear-feedback shift register. Upper layers of the software stack need not be aware that the link layer is using these methods.
Properties and application
64b/66b's design goals are clock recovery, stream alignment, DC balance, transition density and run length. 8b/10b encoding guarantees strict bounds on DC balance, transition density and run length, whereas 64b/66b provides statistical bounds on these properties.
Run length
Most clock recovery circuits designed for SONET OC-192 and 64b/66b are specified to tolerate an 80-bit run length. Such a run cannot occur in 64b/66b because transitions are guaranteed at 66-bit intervals, and in fact long runs are very unlikely. Although it is theoretically possible for a random data pattern to align with the scrambler state and produce a long run of 65 zeroes or 65 ones, the probability of such an event is equal to flipping a fair coin and having it come up in the same state 64 times in a row. At 10 Gigabits per second, the expected event rate of a 66-bit block with a 65-bit run-length, assuming random data, is 66×264÷1010÷2 seconds, or about once every 1900 years.
The run length statistics may get worse if the data consists of specifically chosen patterns, instead of being random. An earlier scrambler used in
64b/66b avoided this vulnerability by using a scrambling polynomial with enough random internal state (58 bits) so that a dedicated attacker using a crafted Ethernet packet can only create a 64-bit run-length in the scrambler output once in about 29 years.[1]: 11–13 This creates 66-bit blocks containing 65-bit runs at a rate similar to using random data.
DC balance
The DC balance of 64b/66b is not absolutely bounded. However, it can be shown that the scrambler output closely approximates a sequence of random binary bits. Passing such a sequence through an AC-coupled circuit produces a
Hamming distance
10 Gigabit Ethernet has a strict charter requiring a Mean Time to False Packet Acceptance (MTTFPA) to be on the order of 1 billion years for a single operating link. To achieve this at normal bit error rates requires at least a 4-bit Hamming distance protection for all packet data. In other words, all combinations of 3 randomly spaced bit-flips within a packet boundary must be detected and result in an invalidated packet. Several strategies were combined to achieve the 4-bit Hamming distance for 64b/66b packets: 1) strong type fields were chosen with 4-bit Hamming distance, 2) the scrambler polynomial was chosen to be compatible with the CRC-32 used for packet protection and 3) protocol violations adjacent to the packet boundaries are required to invalidate the packet. The combination of CRC-32 and the chosen scrambler polynomial were evaluated by exhaustively enumerating all 4-bit error patterns for all possible packet sizes with an optimized C program.
Observations
The main contribution of 64b/66b is the observation that deterministic run length and transition density of 8b/10b are not always worth a 25% code overhead, and that solid robust systems could be designed using statistically bounded methods. At some point, practical risks, whether from MTBF of components such as power supplies or from phenomena such as cosmic rays or solar flares, dominate the reliability of both 8b/10b and 64b/66b systems.
Variations
The Interlaken protocol improves the DC balance further by trading off more coding bits. Its 64b/67b encoding extends 64b/66b with explicit DC balancing. This may be beneficial for some applications, such as using smaller on-chip coupling capacitors.
PCI Express 3.0 introduced 128b/130b encoding, which is similar to 64b/66b but has a payload of 128 bits instead of 64 bits, and uses a different scrambling polynomial: x23 + x21 + x16 + x8 + x5 + x2 + 1. It is also not self-synchronous and so requires explicit synchronization of seed values, in contrast with 64b/66b.
Successors
For each {n}b/{n+2}b encoding, the symbol/data ratio is always below 1. With a ratio of 0.985 for 128b/130b encoding, there is no real margin for improvement.
The following approaches are available to further increase the data rate:
- Higher symbol rates combined with FEC
Very common are 512b/514b encodings combined with Reed–Solomon error correction. The following variants are often used:
- RS(528,514, 7,10), adding 14 correction bits to the 512b/514b code word, allowing to correct up to 7 corrupted bits. Overhead is 3%, same as 64b/66b encoding
- RS(544,514,14,10), adding 30 correction bits to the 512b/514b code word, allowing to correct up to 15 corrupted bits. Overhead is 6%.
The FEC allows symbol error rates of 2.3 · 10−5 or 2.2 · 10−4 to achieve a bit error rate of less than 10−15 in the transmitted data.
- Multi-level encoding combined with FEC
Further improvements are possible by switching from PAM-2 to
- Multi-level Trellis modulationcombined with FEC
Technologies that use 64b/66b encoding
- 100 Gigabit Ethernet
- 10G-EPON, 10 Gbit/s Ethernet Passive Optical Network
- 10 Gigabit Ethernet (most varieties)
- Aurora, from Xilinx
- Camera Link HS
- Common Public Radio Interface
- Fibre Channel 10GFC and 16GFC
- InfiniBand
- Thunderbolt
- JESD204C
Technologies that use 128b/1xxb encoding
- NVLink 1.0
- PCIe 3.x
- PCIe 4.x
- PCIe 5.x
- SATA 3.2
- SAS 4
- USB 3.1 Gen2
- USB4
- DisplayPort 2.0
Technologies that use 256b/257b encoding
- Fibre Channel 32GFC "Gen 6" and higher
References
- ^ R.C. Walker; R. Dugan (January 18–20, 2000). "64b/66b low-overhead coding proposal for serial links" (PDF). IEEE 802.3 High Speed Study Group.
External links
- Note that this is the original proposal to the IEEE, and some changes were made for the final, agreed standard. The circuit diagram for the 58-bit scrambling polynomial described in the proposal is identical to the one adopted in the standard. However, the proposal numbers the registers in reverse order such that the x58+x19+1 polynomial in the proposal is the same as the one labelled x58+x39+1 in the standard.
- US Patent/US6650638: Decoding method and decoder for 64b/66b coded packetized serial data
- US Patent/US6718491: Coding method and coder for packetized serial data with low overhead
- US Patent/US7055073: Coding method for coding packetized serial data with low overhead
- PatentView/EP1133123 Software Patent: 64b/66b decoding, for packetized serial data
- ERROR CORRECTION ON 64/66 BIT ENCODED LINKS
- Introduction to 10 Gigabit 64b/66b (Clause 49)
- A reference design by Xilinx on 64b/66b encoding and scrambling
- Aurora 64B66B IP core using 64b/66b encoding