ARM Cortex-A8
| Cache | |
|---|---|
| L1 cache | 32 KiB/32 KiB |
| L2 cache | 512 KiB |
| Architecture and classification | |
| Instruction set | ARMv7-A |
| Physical specifications | |
| Cores |
|
The ARM Cortex-A8 is a
ARMv7-A architecture
.
Compared to the ARM11, the Cortex-A8 is a dual-issue superscalar design, achieving roughly twice the instructions per cycle. The Cortex-A8 was the first Cortex design to be adopted on a large scale in consumer devices.[2]
Features
Key features of the Cortex-A8 core are:
- Frequency from 600 MHz to 1 GHz and above
- Superscalardual-issue microarchitecture
- SIMD instruction set extension [3]
- 13-stage integer pipeline and 10-stage NEON pipeline [4]
- VFPv3floating-point unit
- Thumb-2instruction set encoding
- Jazelle RCT(also known as ThumbEE instruction set)
- Advanced branch prediction unit with >95% accuracy
- Integrated level 2 Cache (0–4 MiB)
- 2.0 DMIPS/MHz
Chips
Several
system-on-chips
(SoC) have implemented the Cortex-A8 core, including:
- Allwinner A1X
- Apple A4
- Freescale Semiconductor i.MX51 [5]
- Rockchip RK2918, RK2906 [6]
- Samsung Exynos 3110
- TI OMAP3
- TI Sitara ARM Processors
- Conexant CX92755 [7]
See also
- ARM architecture
- Comparison of ARMv7-A cores
- JTAG
- List of applications of ARM cores
- List of ARM cores
References
- ^ "Cortex-A8". ARM Developer. Retrieved January 3, 2023.
- ^ Gupta, Rahul (April 26, 2013). "ARM Cortex: The force that drives mobile devices". The Mobile Indian. Retrieved 2023-07-30.
- ^ Cortex-A8 Specification Summary; ARM Holdings.
- ^ Williamson, David, ARM Cortex A8: A High Performance Processor for Low Power Applications (PDF), archived from the original (PDF) on 2015-01-01
- ^ "i.MX51 Applications Processor and Linux Hands on" (PDF). Archived from the original (PDF) on 2011-11-19. Retrieved 2011-10-20.
- ^ "RK29XX". Archived from the original on 2011-11-05.
- ^ "CX97255" (PDF). Archived from the original (PDF) on 2012-11-19.
External links
- ARM Holdings