ARM Cortex-A77

Source: Wikipedia, the free encyclopedia.
ARM Cortex-A77
General information
Launched2019
Designed by
ARMv8.4-A dot product.
Physical specifications
Cores
  • 1–4 per cluster
Products, models, variants
Product code name(s)
  • Deimos
History
Predecessor(s)ARM Cortex-A76
Successor(s)ARM Cortex-A78, ARM Cortex-X1

The ARM Cortex-A77 is a

ARM Holdings' Austin design centre.[1] ARM announced an increase of 23% and 35% in integer and floating point performance, respectively. Memory bandwidth increased 15% relative to the A76.[1]

Design

The Cortex-A77 serves as the successor of the

superscalar design with a new 1.5K macro-OP (MOPs) cache. It can fetch 4 instructions and 6 Mops per cycle. And rename and dispatch 6 Mops, and 13 μops per cycle. The out-of-order window size has been increased to 160 entries. The backend is 12 execution ports with a 50% increase over Cortex-A76. It has a pipeline depth of 13 stages and the execution latencies of 10 stages.[1][2]

There are six pipelines in the integer cluster – an increase of two additional integer pipelines from Cortex-A76. One of the changes from Cortex-A76 is the unification of the issue queues. Previously each pipeline had its own issue queue. On Cortex-A77, there is now a single unified issue queue which improves efficiency. Cortex-A77 added a new fourth general math ALU with a typical 1-cycle simple math operations and some 2-cycle more complex operations. In total, there are three simple ALUs that perform arithmetic and logical data processing operations and a fourth port which has support for complex arithmetic (e.g. MAC, DIV). Cortex-A77 also added a second branch ALU, doubling the throughput for branches.

There are two ASIMD/FP execution pipelines. This is unchanged from Cortex-A76. What did change is the issue queues. As with the integer cluster, the ASIMD cluster now features a unified issue queue for both pipelines, improving efficiency. As with Cortex-A76, the ASIMD on Cortex-A77 are both 128-bit wide capable of 2 double-precision operations, 4 single-precision, 8 half-precision, or 16 8-bit integer operations. Those pipelines can also execute the cryptographic instructions if the extension is supported (not offered by default and requires an additional license from Arm). Cortex-A77 added a second AES unit in order to improve the throughput of cryptography operations.[3]

Larger ROB, Up to 160-entry, up from 128, Add New L0 MOP cache , can up to 1536-entry.[4]

The core supports

ARMv8-A ISA. It also supports Load acquire (LDAPR) instructions (ARMv8.3-A), Dot Product instructions (ARMv8.4-A), and PSTATE Speculative Store Bypass Safe (SSBS) bit instructions (ARMv8.5-A
).

The Cortex-A77 supports

ARM's DynamIQ technology, and is expected to be used as high-performance cores in combination with Cortex-A55 power-efficient cores.[1]

Architecture changes in comparison with ARM Cortex-A76

  • Front-end[5][6]
    • Branch-prediction
      • Better accuracy
      • Up to 64B runahead window (From 32B)
      • Increase L1 BRB capacity, up to 64-entry (From 16-entry)
      • Increase BTB capacity, up to 8K-entry (From 6K-entry)
    • Improved prefetcher
    • Add new L0 Macro-op cache
    • Wider
      instruction fetch
      , up to 6 instructions/cycle (From 4 instructions/cycle)
  • Execution engine
    • Wider
      instruction fetch
      , Up to 6 instructions/cycle (From 4 instructions/cycle)
    • Larger Re-Order Buffer, Up to 160-entry (From 128-entry)
    • Wider dispatch, up to 10-way, (From 8-way)
    • Wider issue, up to 12-way (From 8-way)
      • Execution units
        • New integer ALU unit and port
        • New branch unit and port
        • New dedicated store data ports
        • New AES unit added

Licensing

The Cortex-A77 is available as

display controller, DSP, image processor, etc.) into one die constituting a system on a chip
(SoC).

Usage

The Samsung

690 respectively.[12][13][14] HiSilicon uses the Cortex-A77 at two different frequencies in their Kirin 9000 series.[15][16]

Both its predecessor (Cortex-A76) and its successor (Cortex-A78) had automotive variants with Split-Lock capability, the Cortex-A76AE and Cortex-A78AE, but the Cortex-A77 did not, thus not finding its way into security critical applications.

See also

References

  1. ^ a b c d Frumusanu, Andrei. "Arm's New Cortex-A77 CPU Micro-architecture: Evolving Performance". www.anandtech.com. Retrieved 2019-06-16.
  2. ^ Schor, David (2019-05-26). "Arm Unveils Cortex-A77, Emphasizes Single-Thread Performance". WikiChip Fuse. Retrieved 2019-06-16.
  3. ^ "Arm Cortex-A77".
  4. ^ "Cortex-A77 - Microarchitectures - ARM - WikiChip". en.wikichip.org. Retrieved 2021-02-06.
  5. ^ "Arm Cortex-A77 - everything you need to know". Android Authority. 2019-05-27. Retrieved 2021-02-08.
  6. ^ "Cortex-A77 - Microarchitectures - ARM - WikiChip". en.wikichip.org. Retrieved 2021-02-08.
  7. ^ "Samsung Introduces its First 5G-Integrated Mobile Processor, the Exynos 980". Samsung Semiconductor. Retrieved 2021-01-11.
  8. ^ "Exynos 980 5G Mobile Processor: Specs, Features | Samsung Exynos". Samsung Semiconductor. Retrieved 2020-06-18.
  9. ^ Frumusanu, Andrei. "Samsung Announces Exynos 980 - Mid-Range With Integrated 5G Modem". www.anandtech.com. Retrieved 2021-01-11.
  10. ^ "Exynos 880 5G Mobile Processor: Specs, Features | Samsung Exynos". Samsung Semiconductor. Retrieved 2021-01-11.
  11. ^ MediaTek (2020-06-18). "MediaTek Dimensity 1000 Series". MediaTek. Retrieved 2020-06-18.
  12. ^ "Qualcomm Snapdragon 865 5G Mobile Platform | Latest Snapdragon Processor". Qualcomm. 2019-11-19. Retrieved 2020-06-18.
  13. ^ "Qualcomm Snapdragon 750G Mobile Platform | Qualcomm". www.qualcomm.com. Retrieved 2021-01-11.
  14. ^ "Snapdragon 690 Mobile Platform". Qualcomm.
  15. ^ "Kirin 9000 Chipset | HiSilicon Official Site". www.hisilicon.com. Retrieved 2023-10-04.
  16. ^ Hinum, Klaus. "HiSilicon Kirin 9000 Processor - Benchmarks and Specs". Notebookcheck. Retrieved 2023-10-04.
Retrieved from "https://en.wikipedia.org/w/index.php?title=ARM_Cortex-A77&oldid=1206138838"