Low-κ dielectric

Source: Wikipedia, the free encyclopedia.

In

interconnects and transistors) from one another. As components have scaled and transistors have gotten closer together, the insulating dielectrics have thinned to the point where charge build up and crosstalk adversely affect the performance of the device. Replacing the silicon dioxide with a low-κ dielectric of the same thickness reduces parasitic capacitance, enabling faster switching speeds (in case of synchronous circuits
) and lower heat dissipation. In conversation such materials may be referred to as "low-k" (spoken "low-kay") rather than "low-κ" (low-kappa).

Low-κ materials

In

integrated circuits, and CMOS devices, silicon dioxide can readily be formed on surfaces of Si through thermal oxidation, and can further be deposited on the surfaces of conductors using chemical vapor deposition or various other thin film fabrication methods. Due to the wide range of methods that can be used to cheaply form silicon dioxide layers, this material is used conventionally as the baseline to which other low permittivity dielectrics are compared. The relative dielectric constant of SiO2, the insulating material still used in silicon chips, is 3.9. This number is the ratio of the permittivity of SiO2 divided by permittivity of vacuum, εSiO2/ε0, where ε0 = 8.854×10−6 pF/μm.[1]
There are many materials with lower relative dielectric constants but few of them can be suitably integrated into a manufacturing process. Development efforts have focused primarily on the following classes of materials:

Fluorine-doped silicon dioxide

Main article: Fluorosilicate glass

By doping SiO2 with fluorine to produce fluorinated silica glass, the relative dielectric constant is lowered from 3.9 to 3.5.

130 nm technology nodes.[3]

Organosilicate glass or OSG (Carbon-doped oxide or CDO)

By doping SiO2 with carbon, one can lower the relative dielectric constant to 3.0, the density to 1.4 g/cm3 and the thermal conductivity to 0.39 W/(m*K). The

90 nm technology node.[4]

Porous silicon dioxide

Various methods may be employed to create voids or pores in a silicon dioxide dielectric.[3] Voids can have a relative dielectric constant of nearly 1, thus the dielectric constant of the porous material may be reduced by increasing the porosity of the film. Relative dielectric constants lower than 2.0 have been reported. Integration difficulties related to porous silicon dioxide implementation include low mechanical strength and difficult integration with etch and polish processes.

Porous organosilicate glass (carbon-doped oxide)

Porous organosilicate materials are usually obtained by a two-step procedure

45 nm technology node.[5]

Spin-on organic polymeric dielectrics

Polymeric dielectrics are generally deposited by a spin-on approach, which is traditionally used for the deposition of

PTFE
.

Spin-on silicon based polymeric dielectric

There are two kinds of silicon based polymeric dielectric materials, hydrogen silsesquioxane and methylsilsesquioxane.

Air gaps

The ultimate low-κ material is air with a relative permittivity value of ~1.0. However, the placement of air gaps between the conducting wires compromises the mechanical stability of the integrated circuit making it impractical to build an IC consisting entirely of air as the insulating material. Nevertheless, the strategic placement of air gaps can improve the chip's electrical performance without compromising critically its durability. For example, Intel uses air gaps for two interconnect levels in its

14 nm FinFET technology.[6]

See also

References

  1. ISBN 978-0-471-14323-9
    .
  2. doi:10.1016/S0167-9317(01)00586-X
    .
  3. ^
    doi:10.1016/S1369-7021(06)71387-6
    .
  4. ^
    doi:10.1016/S1369-7021(04)00053-7
    .
  5. S2CID 32675222
    .
  6. ^ James, Dick. "IEDM – Monday was FinFET Day". Chipworks.com. Retrieved 9 December 2018.

External links

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