Parasitic extraction

In

The major purpose of parasitic extraction is to create an accurate analog model of the circuit, so that detailed simulations can emulate actual digital and analog circuit responses. Digital circuit responses are often used to populate databases for signal delay and loading calculation such as:

Interconnect capacitance is calculated by giving the extraction tool the following information: the top view layout of the design in the form of input polygons on a set of layers; a mapping to a set of devices and pins (from a Layout Versus Schematic run), and a cross sectional understanding of these layers. This information is used to create a set of layout wires that have added capacitors where the input polygons and cross sectional structure indicate. The output netlist contains the same set of input nets as the input design netlist and adds parasitic capacitor devices between these nets.

Interconnect resistance extraction

Interconnect resistance is calculated by giving the extraction tool the following information: the top view layout of the design in the form of input polygons on a set of layers; a mapping to a set of devices and pins (from a Layout Versus Schematic run), and a cross sectional understanding of these layers including the resistivity of the layers. This information is used to create a set of layout sub.wires that have added resistance between various sub-parts of the wires. The above Interconnect Capacitance is divided and shared amongst the sub-nodes in a proportional way. Note that unlike Interconnect Capacitance, Interconnect Resistance needs to add sub-nodes between the circuit elements to place these parasitic resistors. This can greatly increase the size of the extracted output netlist and can cause additional simulation problems.

Interconnect inductance extraction

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Tools and vendors

The tools fall into the following broad categories.

• Field solvers provide physically accurate solutions. They calculate electromagnetic parameters by directly solving Maxwell's equations
  . Due to high calculation burden they are applicable only very small designs or to parts of the designs.
• Approximate solutions with pattern matching techniques are the only feasible approach to extract parasitics for complete modern integrated circuit designs.

Source code and Windows binary versions with viewer and editor are freely available from FastFieldSolvers.^[4][5]

FasterCap

FasterCap, from FastFieldSolvers, is a free, open source capacitance field solver, available for Windows and Linux OS, able to simulate conductive structures embedded in piece-wise-constant, complex permittivity dielectric media, automatic mesh refinement capability and in-core/out-of-core solver engine.

StarRC

StarRC from

Quantus from Cadence is a parasitic extractor tool for both digital and analog designs and parasitics extraction check have to be carried out to prepare the design for postlayout verification.^[7]

QuickCap

QuickCap NX from Synopsys is a parasitic extractor tool for both digital and analog designs.^[8] It was based on QuickCap developed by Ralph Iverson of Random Logic Corporation, which was acquired by Magma and Synopsys.

Calibre xACT3D

Calibre xACT3D from Mentor Graphics is a parasitic extractor tool for both digital and analog designs.^[9] It was based on PexRC developed by Wangqi Qiu and Weiping Shi of Pextra Corporation, which was acquired by Mentor.

See also

• Standard Parasitic Exchange Format

References