Raytheon 704
core memory |
The Raytheon 704 is a
A key feature of the design was the ability to expand the
Another unique feature was that general input/output expansion was external, using a daisy chained cable system known as DIO. This allowed devices like lab equipment and low-speed storage like tape drives to be added without requiring an internal card to support it; the device was added simply by connecting it to the nearest free DIO port on the computer or any other DIO device.
The 704 does not appear to have seen widespread use, although passing mentions can be found in many documents and it had a presence in scientific circles. One example is displaying weather radar data for the United States Air Force.
History
When it was launched, the 704 was a competitive machine compared to recently released systems. The PDP-8/I, of 1968, cost $12,800 for a similar 4 kWord machine, but used smaller 12-bit words and thus had 6 kB of memory compared to the 704's 16-bit words where the same 4 kWord memory was 8 kB. The 704 was also faster, running at 1 MHz rather than the PDP-8's 600 kHz.[6] Another machine aimed more squarely at the 704's instrumentation market was the HP 2116A, another 16-bit design that listed at $22,000.[7]
In spite of these advantages, the 704 faced stiff competition from other newly introduced machines like the Data General Nova, which had a similar feature set but was less expensive, with a similar configuration costing $7,999.[8] The Nova was slower than the 704, but this was addressed in the SuperNOVA, released in 1970 for $11,700. This sandwiched the 704 between lower-cost, lower-performance solutions, and higher-performance solutions that were only slightly more expensive.[9]
The 704 was used as an onsite seismic processing system by Petty-Ray Geophysical, named the Com*MAND 1, in the early 1970s, equipped with 1/2" tape drives, card reader, Teletype 33 console, and Gould 11" electrostatic plotter. Without an ATP,
The successor to the 704 was the RDS 500 which was extensively used by seismic acquisition companies such as Petty-Ray Geophysical, named the Com*MAND 2, CGG (company), Seismograph Survey Company (SSC) and Seismograph Survey Ltd (SSL), as well as several national oil companies.[10]
The compact size and relatively low environmental needs as compared to traditional mainframe systems meant it could be installed in 'frontier' areas in offices and trailers, processing seismic data for fast turnaround behind seismic data acquisition crews operating in areas such as North Africa, the Middle East and the Far East and various active exploration areas in the 1970s.
Description
Hardware design
Like most minicomputers of the late 1960s, the 704 was designed to be mounted in a
The
A showcase feature was the external input/output system, handled using a separate 16-bit wide "data input/output bus", or DIO, with up to 16 devices on two physical ports.[12] These were connected together with custom DIO cables, daisy chained up to 50 feet (15 m) in total. By using both ports on separate 50-foot chains and placing the CPU in the center, the total distance could be up to 100 feet (30 m). The end of every DIO bus had to have an electrical terminator, even if it was unused.[13]
The basic unit included 4 kilowords of 18-bit memory, and a DIO controller for an ASCII terminal, normally the
The purpose of the 18-bit memory was to allow the use of an optional
The hardware multiply/divide card reduced the time for a 16-bit multiply from 105 μsec to only 8, and a divide from 193 to 10.[12]
The DIO normally had a single level of
The
Finally, a Power Failsafe Option was available that was intended to stop the processor in a known-good state if it noticed the
CPU model
The CPU ran lock-step with the core memory, which was a typical design of the era. This limited the machine to a basic 1 μsec cycle time,[17][b] or 1 MHz in common modern terms. The clock was a 20 MHz crystal oscillator that was divided down for the various components.[18]
There were 72 basic instructions, plus the MPY
and DIV
instructions if the multiply/divide unit was installed. Instructions were generally one word long, in strong contrast to typical designs of the era which used variable length instructions depending on the addressing mode. Most instructions used the single user-visible 16-bit accumulator ACR and a 16-bit memory buffer register (MBR) used to temporarily hold operands for two-operand instructions (the other being ACR). 15-bit registers were used for the program counter (PCR) and memory address register (MAR), the later of which was used while fetching data from memory. Addresses could also be offset using the 16-bit index register IXR.[19] Two other registers, the 5-bit EXR and 8-bit INR served special purposes.[20]
Opcodes were generally 4-bits in length, in bits 0 through 3. The purpose of the 15-bit addresses in a 16-bit machine was to set aside one bit in the instruction format to indicate that the address was relative, normally bit 4. This left bits 5 through 15 for use as an address or constant. When used as an address, this meant it was only 11 bits long, and an additional four bits from the 5-bit EXR were added to the front to make a complete 15-bit address. This meant the memory was logically organized as a set of 2 k pages, and working with data in another page required instructions to change the EXR. All five bits of EXR were used when using byte addressing, or only four when addressing words. On top of both, the index register would be added if the index bit was turned on in the instruction.[21]
Math instructions, ADD
and SUB
, always worked on 16-bit values, as did logical operations – AND
, ORI
("inclusive" OR) and ORE
(exclusive OR). Interesting additions were INV
to invert the value and CMP
to perform the two's complement. Shift and rotate instructions were available in 16 and 32-bit forms.[22]
There were three primary comparison operators, CMW
to compare words and CMB
to compare bytes, and CLB
to compare a byte in the accumulator with a literal byte (constant) in the address section of the instruction word. The only other support for literals was LLB
which loaded a constant byte value into the accumulator.[22] These sorts of literal (or constant) instructions are generally much more common in most processors as it avoids a memory accesses for these frequently used instructions.
Conditional branching was not supported directly, instead, there were a series of "skip" instructions that could be performed after a comparison. For instance, SAZ
would skip the next instruction if the value in the accumulator was zero. To perform branches, the next instruction would normally be a jump, JMP
or jump-and-store-address-in-IXR, JSX
, used for subroutines. In addition to the accumulator, skip instructions were provided that read the index register, the results of a comparison and for four of the front-panel switches.[22]
ATP add-on
In January 1971, Raytheon announced a new add-on for the 704 system, the Array Transform Processor, or ATP. This required an entire 3U case of its own. This was essentially a vector processor dedicated to performing fast Fourier transforms (FFT), with arrays from 2 to 8192 complex numbers. A typical 2048 FFT could be accomplished in "only 150 milliseconds!" A system consisting of a 704, the ATP and enough memory to hold the data ran to about $40,000 (equivalent to $300,937 in 2023).[23]
It was this ATP add-on which made the 704 and the later RDS500 so popular as a seismic data processing system, the ATP speeding up the many digital signal processing techniques such as filtering, deconvolution and correlation which were essential in enhancing the seismic data for interpretation.
Notes
References
Citations
- ^ Review 1975, p. 72.
- ^ a b c d Dummer, Thomson & Robertson 1971, p. 805.
- ^ WEATHER RADAR PROCESSOR AND DISPLAY: RADAR INTERFACE ADAPTER, VOLUME II. Raytheon. [1]
- ISBN 978-0-262-03399-2.
- ^ "In Memory of Richard (Rick) F. Loomis 1947–2019: Founder of the Flying Buffalo".
- ^ Jones, Douglas. "The PDP-8/I". University Of Iowa Department of Computer Science.
- ^ Leo Brown, Simon (21 July 2016). "HP museum and its prized 2116a 16-bit computer lives on as legacy of mountaineer Jon Johnston". ABC News Melbourne.
- ^ "The best small computer in the world" (PDF). Computer History Museum. November 1968.
- ^ NOVA/SUPERNOVA (PDF). Data General. February 1970.
- ^ "Advertisement for the RDS 500". Computer World Magazine. 17 September 1975.
- ^ Manual 1970, p. 2.3.
- ^ a b c d Manual 1970, p. 1.1.
- ^ Manual 1970, p. 2.4.
- ^ a b c d Manual 1970, p. 1.3.
- ^ Manual 1970, p. 1.2.
- ^ Manual 1970, p. 2.5.
- ^ Manual 1970, p. 1.5.
- ^ Manual 1970, p. 4.3.
- ^ Manual 1970, p. 4.1.
- ^ Manual 1970, pp. 4.1–4.2.
- ^ Manual 1970, p. 4.67.
- ^ a b c Dummer, Thomson & Robertson 1971, p. 806.
- ^ "Our new ATP gives the Raytheon 704 20 times more power than you bargained for". Analytical Chemistry. January 1971. p. 5A.
Bibliography
- Raytheon 704 Technical Manual (PDF). Raytheon. July 1970.
- Dummer, G. W. A.; Thomson, F. P.; Robertson, J. Mackenzie (1971). Banking Automation: Data Processing Systems and Associated Equipment, Volume 1. Pergamon Press. ISBN 9781483160238.
- Minicomputer Review 1975. GML Corporation. 1975.