Tape-out

In

• Chip finishing which includes custom designations and structures to improve
  manufacturability
  of the layout. Examples of the latter are a seal ring and filler structures.
• Producing a reticle layout with test patterns and alignment marks.[2]
• Layout-to-mask preparation that enhances layout data with graphics operations and adjusts the data to mask production devices. This step includes resolution enhancement technologies (RET), such as optical proximity correction (OPC) which corrects for the wave-like behavior of light when etching the nano scale features of the most modern integrated circuits.^[1]

A modern IC has to go through a long and complex design process before it is ready for tape-out. Many of the steps along the way use software tools collectively known as

First tapeout is rarely the end of work for the design team. Most chips will go through a series of iterations, called "spins", in which errors are detected and fixed after testing the first article. Many different factors can cause a spin, including:

• The taped-out design fails final checks at the foundry due to problems manufacturing the design itself.
• The design is successfully fabricated, but the first article fails functionality tests.

Naming

The roots of the term can be traced back to the time when paper tape and later magnetic tape reels were loaded with the final electronic files used to create the photomask at the factory.^[1][3][4]

A synonym used at IBM is RIT (release interface tape). IBM differentiates between RIT-A for the non-metallic structures and RIT-B for the metal layers.^[5]

See also

• Mask data preparation
• Semiconductor fabrication
• GDSII

References