UltraSPARC
This article includes a SPARC V9 | |
Physical specifications | |
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Cores |
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History | |
Predecessor(s) | SuperSPARC II |
Successor(s) | UltraSPARC II |
The UltraSPARC is a
Microarchitecture
The UltraSPARC is a four-issue
Functional units
The execution units were simplified relative to the SuperSPARC to achieve higher clock frequencies - an example of a simplification is that the ALUs were not cascaded, unlike the SuperSPARC, to avoid restricting clock frequency.
The integer register file has 32 64-bit entries. As the SPARC ISA uses register windows, of which the UltraSPARC has eight, the actual number of registers is 144. The register file has seven read and three write ports. The integer register file provides registers to two arithmetic logic units and the load/store unit. The two ALUs can both execute arithmetic, logic and shift instructions but only one can execute multiply and divide instructions.
The floating-point unit consists of five functional units. One executes floating point adds and subtracts, one multiplies, one divides and square-roots. Two units are for executing SIMD instructions defined by the Visual Instruction Set (VIS). The floating-point register file contains thirty-two 64-bit registers. It has five read ports and three write ports.
Cache
The UltraSPARC has two levels of cache, primary and secondary. There are two primary caches, one for instructions and one for data. Both have a capacity of 16 KB.
The UltraSPARC required a mandatory external secondary cache. The cache is unified, has a capacity of 512 KB to 4 MB and is direct-mapped. It can return data in a single cycle. The external cache is implemented with synchronous SRAMs clocked at the same frequency as the microprocessor, as ratios were not supported. It is accessed via the data bus.
Fabrication
It contained 3.8 million transistors. It was fabricated in Texas Instruments' EPIC-3 process, a 0.5 μm
Package
The UltraSPARC is packaged in a 521-contact plastic ball grid array (PBGA).
Related processors
References
- Greenley, D. et al. (1995). "UltraSPARC: The next generation superscalar 64-bit SPARC". Proceedings of Compcon '95: pp. 442–451.
- Gwennap, Linley (3 October 1994). "UltraSparc Unleashes SPARC Performance". Microprocessor Report, Volume 8, Number 13.
- Gwennap, Linley (5 December 1994). "UltraSparc Adds Multimedia Instructions". Microprocessor Report.