Digital signal processor
A digital signal processor (DSP) is a specialized
The goal of a DSP is usually to measure, filter or compress continuous real-world
Overview
Digital signal processing (DSP) algorithms typically require a large number of mathematical operations to be performed quickly and repeatedly on a series of data samples. Signals (perhaps from audio or video sensors) are constantly converted from analog to digital, manipulated digitally, and then converted back to analog form. Many DSP applications have constraints on latency; that is, for the system to work, the DSP operation must be completed within some fixed time, and deferred (or batch) processing is not viable.
Most general-purpose microprocessors and operating systems can execute DSP algorithms successfully, but are not suitable for use in portable devices such as mobile phones and PDAs because of power efficiency constraints.[5] A specialized DSP, however, will tend to provide a lower-cost solution, with better performance, lower latency, and no requirements for specialised cooling or large batteries.[citation needed]
Such performance improvements have led to the introduction of digital signal processing in commercial
The architecture of a DSP is optimized specifically for digital signal processing. Most also support some of the features of an applications processor or microcontroller, since signal processing is rarely the only task of a system. Some useful features for optimizing DSP algorithms are outlined below.
Architecture
Software architecture
By the standards of general-purpose processors, DSP instruction sets are often highly irregular; while traditional instruction sets are made up of more general instructions that allow them to perform a wider variety of operations, instruction sets optimized for digital signal processing contain instructions for common mathematical operations that occur frequently in DSP calculations. Both traditional and DSP-optimized instruction sets are able to compute any arbitrary operation but an operation that might require multiple ARM or x86 instructions to compute might require only one instruction in a DSP optimized instruction set.
One implication for software architecture is that hand-optimized
Instruction sets
- fused multiply–add, FMA) operations
- used extensively in all kinds of matrix operations
- convolution for filtering
- dot product
- polynomial evaluation
- Fundamental DSP algorithms depend heavily on multiply–accumulate performance
- used extensively in all kinds of matrix operations
- related instructions:
- SIMD
- VLIW
- Specialized instructions for modulo addressing in ring buffers and bit-reversed addressing mode for FFT cross-referencing
- DSPs sometimes use time-stationary encoding to simplify hardware and increase coding efficiency.[citation needed]
- Multiple arithmetic units may require memory architectures to support several accesses per instruction cycle – typically supporting reading 2 data values from 2 separate data buses and the next instruction (from the instruction cache, or a 3rd program memory) simultaneously.[7][8][9][10]
- Special loop controls, such as architectural support for executing a few instruction words in a very tight loop without overhead for instruction fetches or exit testing—such as zero-overhead looping[11][12] and hardware loop buffers.[13][14]
Data instructions
- Saturation arithmetic, in which operations that produce overflows will accumulate at the maximum (or minimum) values that the register can hold rather than wrapping around (maximum+1 doesn't overflow to minimum as in many general-purpose CPUs, instead it stays at maximum). Sometimes various sticky bits operation modes are available.
- Fixed-point arithmetic is often used to speed up arithmetic processing.
- Single-cycle operations to increase the benefits of pipelining.
Program flow
- Floating-point unit integrated directly into the datapath
- Pipelined architecture
- Highly parallel multiplier–accumulators(MAC units)
- Hardware-controlled looping, to reduce or eliminate the overhead required for looping operations
Hardware architecture
Memory architecture
DSPs are usually optimized for streaming data and use special memory architectures that are able to fetch multiple data or instructions at the same time, such as the Harvard architecture or Modified von Neumann architecture, which use separate program and data memories (sometimes even concurrent access on multiple data buses).
DSPs can sometimes rely on supporting code to know about cache hierarchies and the associated delays. This is a tradeoff that allows for better performance[clarification needed]. In addition, extensive use of DMA is employed.
Addressing and virtual memory
DSPs frequently use multi-tasking operating systems, but have no support for
- Hardware modulo addressing
- Allows circular buffers to be implemented without having to test for wrapping
- Bit-reversed addressing, a special addressing mode
- useful for calculating FFTs
- Exclusion of a memory management unit
- Address generation unit
History
Development
In 1976, Richard Wiggins proposed the
In 1978,
In 1979, Intel released the 2920 as an "analog signal processor".[19] It had an on-chip ADC/DAC with an internal signal processor, but it didn't have a hardware multiplier and was not successful in the market.
In 1980, the first stand-alone, complete DSPs –
The Altamira DX-1 was another early DSP, utilizing quad integer pipelines with delayed branches and branch prediction.[citation needed]
Another DSP produced by Texas Instruments (TI), the
About five years later, the second generation of DSPs began to spread. They had 3 memories for storing two operands simultaneously and included hardware to accelerate tight loops; they also had an addressing unit capable of loop-addressing. Some of them operated on 24-bit variables and a typical model only required about 21 ns for a MAC. Members of this generation were for example the AT&T DSP16A or the Motorola 56000.
The main improvement in the third generation was the appearance of application-specific units and instructions in the data path, or sometimes as coprocessors. These units allowed direct hardware acceleration of very specific but complex mathematical problems, like the Fourier-transform or matrix operations. Some chips, like the Motorola MC68356, even included more than one processor core to work in parallel. Other DSPs from 1995 are the TI TMS320C541 or the TMS 320C80.
The fourth generation is best characterized by the changes in the instruction set and the instruction encoding/decoding. SIMD extensions were added, and VLIW and the superscalar architecture appeared. As always, the clock-speeds have increased; a 3 ns MAC now became possible.
Modern DSPs
Modern signal processors yield greater performance; this is due in part to both technological and architectural advancements like lower design rules, fast-access two-level cache, (E)DMA circuitry, and a wider bus system. Not all DSPs provide the same speed and many kinds of signal processors exist, each one of them being better suited for a specific task, ranging in price from about US$1.50 to US$300.
XMOS produces a multi-core multi-threaded line of processor well suited to DSP operations, They come in various speeds ranging from 400 to 1600 MIPS. The processors have a multi-threaded architecture that allows up to 8 real-time threads per core, meaning that a 4 core device would support up to 32 real time threads. Threads communicate between each other with buffered channels that are capable of up to 80 Mbit/s. The devices are easily programmable in C and aim at bridging the gap between conventional micro-controllers and FPGAs
CSR produces the Quatro family of SoCs that contain one or more custom Imaging DSPs optimized for processing document image data for scanner and copier applications.
Microchip Technology produces the PIC24 based dsPIC line of DSPs. Introduced in 2004, the dsPIC is designed for applications needing a true DSP as well as a true microcontroller, such as motor control and in power supplies. The dsPIC runs at up to 40MIPS, and has support for 16 bit fixed point MAC, bit reverse and modulo addressing, as well as DMA.
Most DSPs use fixed-point arithmetic, because in real world signal processing the additional range provided by floating point is not needed, and there is a large speed benefit and cost benefit due to reduced hardware complexity. Floating point DSPs may be invaluable in applications where a wide dynamic range is required. Product developers might also use floating point DSPs to reduce the cost and complexity of software development in exchange for more expensive hardware, since it is generally easier to implement algorithms in floating point.
Generally, DSPs are dedicated integrated circuits; however DSP functionality can also be produced by using field-programmable gate array chips (FPGAs).
Embedded general-purpose RISC processors are becoming increasingly DSP like in functionality. For example, the
In Communications a new breed of DSPs offering the fusion of both DSP functions and H/W acceleration function is making its way into the mainstream. Such Modem processors include ASOCS ModemX and CEVA's XC4000.
In May 2018, Huarui-2 designed by Nanjing Research Institute of Electronics Technology of
See also
- Digital signal controller
- Graphics processing unit
- System on a chip
- Hardware acceleration
- Vision processing unit
- MDSP – a multiprocessor DSP
- OpenCL
- Sound card
References
- OL 10070096M.
- ISBN 978-0849310812 – via Google Books.
- ^ a b c d e "1979: Single Chip Digital Signal Processor Introduced". The Silicon Engine. Computer History Museum. Retrieved 14 October 2019.
- ^ a b c Taranovich, Steve (August 27, 2012). "30 years of DSP: From a child's toy to 4G and beyond". EDN. Retrieved 14 October 2019.
- ^ a b Ingrid Verbauwhede; Patrick Schaumont; Christian Piguet; Bart Kienhuis (2005-12-24). "Architectures and Design techniques for energy efficient embedded DSP and multimedia processing" (PDF). rijndael.ece.vt.edu. Retrieved 2017-06-13.
- ^ Beyond Frontiers Broadgate Publications (September 2016) pp22
- ^ "Memory and DSP Processors".
- ^ ""DSP processors: memory architectures"". Archived from the original on 2020-02-17. Retrieved 2020-03-03.
- ^ "Architecture of the Digital Signal Processor"
- ^ "ARC XY Memory DSP Option".
- ^ "Zero Overhead Loops".
- ^ "ADSP-BF533 Blackfin Processor Hardware Reference". p. 4-15.
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- ^ "Techniques for Effectively Exploiting a Zero Overhead Loop Buffer".
- ^ "Speak & Spell, the First Use of a Digital Signal Processing IC for Speech Generation, 1978". IEEE Milestones. IEEE. Retrieved 2012-03-02.
- ^ Bogdanowicz, A. (2009-10-06). "IEEE Milestones Honor Three". The Institute. IEEE. Archived from the original on 2016-03-04. Retrieved 2012-03-02.
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- ^ Alberto Luis Andres. "Digital Graphic Audio Equalizer". p. 48.
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