Larrabee (microarchitecture)

Larrabee is the

Almost a decade later, on June 12, 2018; the idea of an Intel dedicated GPU was revived again with Intel's desire to create a discrete GPU by 2020.^[6] This project would eventually become the Intel Xe and Intel Arc series, released in September 2020 and March 2022, respectively - but both were unconnected to the work on the Larrabee project.

Project status

On December 4, 2009, Intel officially announced that the first-generation Larrabee would not be released as a consumer GPU product.^[7] Instead, it was to be released as a development platform for graphics and high-performance computing. The official reason for the strategic reset was attributed to delays in hardware and software development.^[8] On May 25, 2010, the Technology@Intel blog announced that Larrabee would not be released as a GPU, but instead would be released as a product for high-performance computing competing with the Nvidia Tesla.^[9]

The project to produce a GPU retail product directly from the Larrabee research project was terminated in May 2010.

Larrabee can be considered a hybrid between a

As a GPU, Larrabee would have supported traditional rasterized

Differences with contemporary GPUs

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Larrabee was intended to differ from older discrete GPUs such as the

Radeon 4000 series

in three major ways:

• It was to use the x86 instruction set with Larrabee-specific extensions.^[14]
• It was to feature
  cache coherency across all its cores.^[14]
• It was to include very little specialized graphics hardware, instead performing tasks like z-buffering, clipping, and blending in software, using a
  tile-based rendering approach.^[14]

More recent GPUs such as ATI's Radeon HD 5xxx and Nvidia's GeForce 400 series feature increasingly broad general-purpose computing capabilities via DirectX11 DirectCompute and OpenCL, as well as Nvidia's proprietary CUDA technology, giving them many of the capabilities of Larrabee.

Differences with CPUs

The x86 processor cores in Larrabee differed in several ways from the cores in current Intel CPUs such as the

• Its x86 cores were based on the much simpler
  superscalar but does not include out-of-order execution, though it has been updated with modern features such as x86-64 support,^[14] similar to the Bonnell microarchitecture used in Atom
  . In-order execution means lower performance for individual cores, but since they are smaller, more can fit on a single chip, increasing overall throughput. Execution is also more deterministic so instruction and task scheduling can be done by the compiler.
• Each core contained a 512-bit
  scatter/gather instructions and a mask register designed to make using the vector unit easier and more efficient. Larrabee was to derive most of its number-crunching power from these vector units.^[14]
• It included one major
  texture sampling units. These perform trilinear and anisotropic filtering and texture decompression.^[14]
• It had a 1024-bit (512-bit each way) ring bus for communication between cores and to memory.[14] This bus can be configured in two modes to support Larrabee products with 16 cores or more, or fewer than 16 cores.^[16]
• It included explicit cache control instructions to reduce
  cache thrashing during streaming operations which only read/write data once.^[14]
  Explicit prefetching into L2 or L1 cache is also supported.
• Each core supported four-way interleaved multithreading, with four copies of each processor register.^[14]

Theoretically Larrabee's x86 processor cores would have been able to run existing PC software, or even operating systems. A different version of the processor might sit in motherboard CPU sockets using QuickPath,^[17] but Intel never announced any plans for this. Though Larrabee's native C/C++ compiler included auto-vectorization and many applications were able to execute correctly after having been recompiled, maximum efficiency was expected to have required code optimization using C++ vector intrinsics or inline Larrabee assembly code.^[14] However, as in all GPGPUs, not all software would have benefited from utilization of a vector processing unit. One tech journalism site claims that Larrabee's graphics capabilities were planned to be integrated in CPUs based on the Haswell microarchitecture.^[18]

Comparison with the Cell broadband engine

Larrabee's philosophy of using many small, simple cores was similar to the ideas behind the

• The Cell processor includes one main processor which controls many smaller processors. Additionally, the main processor can run an operating system. In contrast, all of Larrabee's cores are the same, and the Larrabee was not expected to run an OS.
• Each computer core in the Cell (
  MOV) instructions. Larrabee cores each had 256 KB of local L2 cache, and an access which hits another L2 segment takes longer to access.^[14]
• Because of the cache coherency noted above, each program running in Larrabee had virtually a large linear memory just as in traditional general-purpose CPU; whereas an application for Cell should be programmed taking into consideration limited
  this article) but with theoretically higher bandwidth. However, since local L2 is faster to access, an advantage can still be gained from using Cell-style programming methods.^{[citation needed}
  ]
• Cell uses
  DMA for data transfer to and from on-chip local memories, which enables explicit maintenance of overlays stored in local memory to bring memory closer to the core and reduce access latencies, but requiring additional effort to maintain coherency with main memory; whereas Larrabee used a coherent cache with special instructions for cache manipulation (notably cache eviction hints and pre-fetch instructions), which mitigated miss and eviction penalties and reduce cache pollution (e.g. for rendering pipelines and other stream-like computation) at the cost of additional traffic and overhead to maintain cache coherency.^[14]
• Each compute core in the Cell runs only one thread at a time, in-order. A core in Larrabee ran up to four threads, but only one at a time. Larrabee's hyperthreading helped hide the latencies inherent to in-order execution. ^[citation needed]

Comparison with Intel GMA

Intel began integrating a line of GPUs onto motherboards under the

The Intel Visual Computing Institute will research basic and applied technologies that could be applied to Larrabee-based products.[22]

Projected performance data

Intel's

The last statement of performance can be calculated (theoretically this is maximum possible performance) as follows: 32 cores × 16 single-precision float SIMD/core × 2 FLOP (fused multiply-add) × 2 GHz = 2 TFLOPS theoretically.

Public demonstrations

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A public demonstration of the Larrabee ray-tracing capabilities took place at the Intel Developer Forum in San Francisco on September 22, 2009. An experimental version of Enemy Territory: Quake Wars titled Quake Wars: Ray Traced was shown in real-time. The scene contained a ray traced water surface that reflected the surrounding objects, like a ship and several flying vehicles, accurately.^[25][26][27]

A second demo was given at the SC09 conference in Portland at November 17, 2009 during a keynote by Intel CTO Justin Rattner. A Larrabee card was able to achieve 1006 GFLops in the SGEMM 4Kx4K calculation.

An engineering sample of a Larrabee card was procured and reviewed by Linus Sebastian in a video published May 14, 2018. He was unable to make the card give video output however, with the motherboard displaying POST code D6.^[28] In 2022 another card was demonstrated by YouTuber Roman “der8auer” Hartung, which was shown to be working and outputting a display signal but was not capable of 3D acceleration due to missing drivers.^[29]

See also

• Xeon Phi
• Intel740
• Intel GMA
• x86
• x86-64
• P5 (microarchitecture)
• Bonnell (microarchitecture)
• List of Intel CPU microarchitectures
• Intel MIC
• Nvidia Tesla
• AMD Accelerated Processing Unit
• AVX-512

References

External links

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• Video of a raytracer running on one of the first Larrabee cards at IDF '09
• Whitepapers on LRBni, Physics Simulations and more using Larrabee
• Rasterization on Larrabee
• A First Look at the Larrabee New Instructions (LRBni)
• C++ implementation of the Larrabee new instructions
• Game Physics Performance on Larrabee
• Intel fact sheet about Larrabee
• Intel's SIGGRAPH 2008 paper on Larrabee
• Techgage.com - Discusses how Larrabee differs from normal GPUs, includes block diagram illustration
• Intel's Larrabee Architecture Disclosure: A Calculated First Move