Contamination delay
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For a sequential circuit such as two D-flip flops connected in series, the contamination delay of the first flip-flop must be factored in to avoid violating the hold-time constraint of the second flip-flop receiving the output from the first flip flop. Here, the contamination delay is the amount of time needed for a change in the flip-flop clock input to result in the initial change at the flip-flop output (Q). If there is insufficient delay from the output of the first flip-flop to the input of the second, the input may change before the hold time has passed. Because the second flip-flop is still unstable, its data would then be "contaminated." Every path from an input to an output can be characterized with a particular contamination delay.
Well-balanced circuits will have similar speeds for all paths through a combinational stage, so the minimum propagation time is close to the maximum. This corresponding maximum time is the propagation delay. The condition of data being contaminated is called a race.
References
- Tessier, Russell (Fall 2003). "Understanding Sequential Circuit Timing" (PDF). Department of Computer and Electrical Engineering, University of Massachusetts Amherst. Archived from the original (PDF) on 2016-03-03.
- "Spring 2004 handout L04-4, Computation Structures (class 6.004)" (PDF). MIT Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology. Archived (PDF) from the original on 2019-08-12.
- Digital Design and Computer Architecture 2nd edition, David Money Harris and Sarah L. Harris, ISBN 9780123944245, Morgan Kaufmann, 2012