Field-programmable analog array

Source: Wikipedia, the free encyclopedia.

A field-programmable analog array (FPAA) is an

summers or integrators
.

FPAAs usually operate in one of two modes: continuous time and discrete time.

  • Discrete-time devices possess a system sample clock. In a switched capacitor design, all blocks sample their input signals with a sample and hold circuit composed of a semiconductor switch and a capacitor. This feeds a programmable op amp section which can be routed to a number of other blocks. This design requires more complex semiconductor construction. An alternative, switched-current design, offers simpler construction and does not require the input capacitor, but can be less accurate, and has lower fan-out - it can drive only one following block. Both discrete-time device types must compensate for switching noise, aliasing at the system sample rate, and sample-rate limited bandwidth, during the design phase.
  • Continuous-time devices work more like an array of
    parasitic inductance, capacitance and noise
    contributions must be taken into account.

Currently there are very few manufactures of FPAAs. On-chip resources are still very limited when compared to that of an

FPGA
. This resource deficit is often cited by researchers as a limiting factor in their research.

History

The LYAPUNOV-1 uses a 4x8 grid of FPAA chips.

The term FPAA was first used in 1991 by Lee and Gulak.[3] They put forward the concept of CABs that are connected via a routing network and configured digitally. Subsequently, in 1992[citation needed] and 1995[4] they further elaborated the concept with the inclusion of op-amps, capacitors, and resistors. This original chip was manufactured using 1.2 μm CMOS technology and operates in the 20 kHz range at a power consumption of 80 mW.

Pierzchala et al introduced a similar concept named electronically-programmable analog circuit (EPAC).[5] It featured only a single integrator. However, they proposed a local interconnect architecture in order to try to avoid the bandwidth limitations.

The reconfigurable analog signal processor (RASP) and a second version were introduced in 2002 by Hall et al.[6][7] Their design incorporated high-level elements such as second order bandpass filters and 4 by 4 vector matrix multipliers into the CABs. Because of its architecture, it is limited to around 100 kHz and the chip itself is not able to support independent reconfiguration.

In 2004 Joachim Becker picked up the

parallel connection of OTAs (operational transconductance amplifiers) and proposed its use in a hexagonal local interconnection architecture.[8]
It did not require a routing network and eliminated switching the signal path that enhances the frequency response.

In 2005 Fabian Henrici worked with Joachim Becker to develop a switchable and invertible OTA which doubled the maximum FPAA bandwidth.

0.13 μm CMOS
technology.

In 2016 Dr. Jennifer Hasler from Georgia Tech designed a FPAA system on a chip that uses analog technology to achieve unprecedented power and size reductions.[10]

See also

References

  1. S2CID 17212868
    .
  2. S2CID 16583629
    .
  3. S2CID 5323561
    .
  4. S2CID 56613166
    .
  5. S2CID 60724962
    .
  6. S2CID 596774
    .
  7. S2CID 1148361
    .
  8. CiteSeerX 10.1.1.444.8748.[clarification needed
    ]
  9. CiteSeerX 10.1.1.444.8748.[clarification needed
    ]
  10. S2CID 14027246
    .

External links
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