Clock signal

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Clock signal and legend

In

synchronous logic circuit, the most common type of digital circuit, the clock signal is applied to all storage devices, flip-flops and latches, and causes them all to change state simultaneously, preventing race conditions
.

A clock

signal is produced by an electronic oscillator called a clock generator. The most common clock signal is in the form of a square wave with a 50% duty cycle. Circuits using the clock signal for synchronization may become active at either the rising edge, falling edge, or, in the case of double data rate
, both in the rising and in the falling edges of the clock cycle.

Digital circuits

Most

asynchronous CPUs
.

A clock signal might also be gated, that is, combined with a controlling signal that enables or disables the clock signal for a certain part of a circuit. This technique is often used to save power by effectively shutting down portions of a digital circuit when they are not in use, but comes at a cost of increased complexity in timing analysis.

Single-phase clock

Most modern synchronous circuits use only a "single phase clock" – in other words, all clock signals are (effectively) transmitted on a single wire.

Two-phase clock

In

edge-triggered flip-flops can be used to store state information
so long as the inputs to latches on one phase only depend on outputs from latches on the other phase. Since a gated latch uses only four gates versus six gates for an edge-triggered flip-flop, a two phase clock can lead to a design with a smaller overall gate count but usually at some penalty in design difficulty and performance.

Metal oxide semiconductor (MOS) ICs typically used dual clock signals (a two-phase clock) in the 1970s. These were generated externally for both the Motorola 6800 and Intel 8080 microprocessors.[6] The next generation of microprocessors incorporated the clock generation on chip. The 8080 uses a 2 MHz clock but the processing throughput is similar to the 1 MHz 6800. The 8080 requires more clock cycles to execute a processor instruction. Due to their dynamic logic, the 6800 has a minimum clock rate of 100 kHz and the 8080 has a minimum clock rate of 500 kHz. Higher speed versions of both microprocessors were released by 1976.[7]

The

6501 requires an external 2-phase clock generator. The MOS Technology 6502
uses the same 2-phase logic internally, but also includes a 2-phase clock generator on-chip, so it only needs a single phase clock input, simplifying system design.

4-phase clock

See also: Four-phase logic

Some early integrated circuits use

Texas Instruments TMS9900, and the Western Digital MCP-1600 chipset used in the DEC LSI-11
.

Four phase clocks have only rarely been used in newer CMOS processors such as the DEC WRL MultiTitan microprocessor.[9] and in Intrinsity's Fast14 technology. Most modern microprocessors and microcontrollers use a single-phase clock.

Clock multiplier

Main article:
Clock multiplier

Many modern

clock multiplier" which multiplies a lower frequency external clock to the appropriate clock rate of the microprocessor. This allows the CPU to operate at a much higher frequency than the rest of the computer, which affords performance gains in situations where the CPU does not need to wait on an external factor (like memory or input/output
).

Dynamic frequency change

The vast majority of digital devices do not require a clock at a fixed, constant frequency. As long as the minimum and maximum clock periods are respected, the time between clock edges can vary widely from one edge to the next and back again. Such digital devices work just as well with a clock generator that dynamically changes its frequency, such as

static logic
do not even have a maximum clock period (or in other words, minimum clock frequency); such devices can be slowed and paused indefinitely, then resumed at full clock speed at any later time.

Other circuits

Some sensitive

single-ended signal
with the same voltage range. Differential signals radiate less strongly than a single line. Alternatively, a single line shielded by power and ground lines can be used.

In CMOS circuits, gate capacitances are charged and discharged continually. A capacitor does not dissipate energy, but energy is wasted in the driving transistors. In reversible computing, inductors can be used to store this energy and reduce the energy loss, but they tend to be quite large. Alternatively, using a sine wave clock, CMOS transmission gates and energy-saving techniques, the power requirements can be reduced.[citation needed]

Distribution

The most effective way to get the clock signal to every part of a chip that needs it, with the lowest skew, is a metal grid. In a large microprocessor, the power used to drive the clock signal can be over 30% of the total power used by the entire chip. The whole structure with the gates at the ends and all amplifiers in between have to be loaded and unloaded every cycle.[10][11] To save energy, clock gating temporarily shuts off part of the tree.

The clock distribution network (or clock tree, when this network forms a tree such as an

H-tree) distributes the clock signal(s) from a common point to all the elements that need it. Since this function is vital to the operation of a synchronous system, much attention has been given to the characteristics of these clock signals and the electrical networks
used in their distribution. Clock signals are often regarded as simple control signals; however, these signals have some very special characteristics and attributes.

Clock signals are typically loaded with the greatest

race conditions
in which an incorrect data signal may latch within a register.

Most synchronous digital systems consist of cascaded banks of sequential registers with combinational logic between each set of registers. The functional requirements of the digital system are satisfied by the logic stages. Each logic stage introduces delay that affects timing performance, and the timing performance of the digital design can be evaluated relative to the timing requirements by a timing analysis. Often special considerations must be given in order to meet the timing requirements. For example, the global performance and local timing requirements may be satisfied by the careful insertion of pipeline registers into equally spaced time windows to satisfy critical worst-case timing constraints. A proper design of the clock distribution network helps ensure that critical timing requirements are satisfied and that no race conditions exist (see also clock skew).

The delay components that make up a general synchronous system are composed of three individual subsystems: the memory storage elements, the logic elements, and the clocking circuitry and distribution network.

Novel structures are currently under development to ameliorate these issues and provide effective solutions. Important areas of research include resonant clocking techniques ("resonant clock mesh"),[12][13][14][15] on-chip optical interconnect, and local synchronization methodologies.

See also

References

  1. Ferranti Limited, Digital Systems Department. October 1968 [September 1968]. List DSD 68/6. Archived
    (PDF) from the original on 2020-05-19. Retrieved 2020-05-19.
  2. ^ Two-phase clock Archived November 9, 2007, at the Wayback Machine
  3. ^ Two-phase non-overlapping clock generator, Tams-www.informatik.uni-hamburg.de, archived from the original on 2011-12-26, retrieved 2012-01-08
  4. ^ Concepts in Digital Imaging - Two Phase CCD Clocking, Micro.magnet.fsu.edu, retrieved 2012-01-08
  5. ^ Cell cgf104: Two phase non-overlapping clock generator, Hpc.msstate.edu, archived from the original on 2012-02-08, retrieved 2012-01-08
  6. ^ "How to drive a microprocessor". Electronics. 49 (8). New York: McGraw-Hill: 159. April 15, 1976. Motorola's Component Products Department sold hybrid ICs that included a quartz oscillator. These IC produced the two-phase non-overlapping waveforms the 6800 and 8080 required. Later Intel produced the 8224 clock generator and Motorola produced the MC6875. The Intel 8085 and the Motorola 6802 include this circuitry on the microprocessor chip.
  7. ^ "Intel's Higher Speed 8080 μP" (PDF). Microcomputer Digest. 2 (3). Cupertino CA: Microcomputer Associates: 7. September 1975. Archived from the original (PDF) on 2019-01-23. Retrieved 2011-01-24.
  8. ^ Concepts in digital imaging - Four Phase CCD Clocking, Micro.magnet.fsu.edu, retrieved 2012-01-08
  9. ^
    doi:10.1109/JSSC.1989.572612
    .
  10. ^ Anand Lal Shimpi (2008), Intel's Atom Architecture: The Journey Begins
  11. ^ Paul V. Bolotoff (2007), Alpha: The history in facts and comments, archived from the original on 2012-02-18, retrieved 2012-01-03, power consumed by the clock subsystem of EV6 was about 32% of the total core power. To compare, it was about 25% for EV56, about 37% for EV5 and about 40% for EV4.
  12. ^ Chan, S. C.; Shepard, K. L.; Restle, P. J. (2005). "Uniform-phase uniform-amplitude resonant-load global clock distributions". IEEE Journal of Solid-State Circuits. 40 (1): 102.
    S2CID 16239014
    .
  13. ^ David Shan et. al. "Resonant clock mega-mesh for the IBM z13". 2015.
  14. ^ Wulong Liu; Guoqing Chen; Yu Wang; Huazhong Yang. "Modeling and optimization of low power resonant clock mesh". 2015.
  15. ^ "Clock tree synthesis".

Further reading

Adapted from Eby Friedman Archived 2014-08-12 at the Wayback Machine's column in the ACM SIGDA e-newsletter by Igor Markov
Original text is available at https://web.archive.org/web/20100711135550/http://www.sigda.org/newsletter/2005/eNews_051201.html

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