Network on a chip

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A network on a chip or network-on-chip (NoC

computer system, and are designed to be modular in the sense of network science. The network on chip is a router-based packet switching network between SoC modules
.

NoC technology applies the theory and methods of computer networking to on-chip communication and brings notable improvements over conventional bus and crossbar communication architectures. Networks-on-chip come in many network topologies, many of which are still experimental as of 2018. [citation needed]

In 2000s, researchers had started to propose a type of on-chip interconnection in the form of

multicore
computer architectures become more common.

Structure

NoCs can span synchronous and asynchronous clock domains, known as

clock domain.[4]

Architectures

NoC architectures typically model

power consumption of interconnection wires and point-to-point
connections.

Topology

The topology determines the physical layout and connections between nodes and channels. The message traverses hops, and each hop's channel length depends on the topology. The topology significantly influences both latency and power consumption. Furthermore, since the topology determines the number of alternative paths between nodes, it affects the network traffic distribution, and hence the network bandwidth and performance achieved.[5]

Benefits

Traditionally, ICs have been designed with dedicated

clock cycles. This also allows more parasitic capacitance, resistance and inductance to accrue on the circuit. (See Rent's rule
for a discussion of wiring requirements for point-to-point connections).

Sparsity and locality of interconnections in the communications subsystem yield several improvements over traditional bus-based and crossbar-based systems.

Parallelism and scalability

The wires in the links of the network-on-chip are shared by many

which?] must be designed in such a way that they offer large parallelism
and can hence utilize the potential of NoC.

Current research

WiNoC in the 3D-chiplet

Some researchers[

throughput, end-to-end delays, fairness,[6] and deadlines.[citation needed] Real-time computation, including audio and video playback, is one reason for providing QoS support. However, current system implementations like VxWorks, RTLinux or QNX are able to achieve sub-millisecond real-time computing without special hardware.[citation needed
]

This may indicate that for many

chip multiprocessor in a public cloud computing infrastructure. In such instances, hardware QoS logic enables the service provider to make contractual guarantees on the level of service that a user receives, a feature that may be deemed desirable by some corporate or government clients.[citation needed
]

Many challenging research problems remain to be solved at all levels, from the physical link level through the network level, and all the way up to the system architecture and application software. The first dedicated research symposium on networks on chip was held at Princeton University, in May 2007.[7] The second IEEE International Symposium on Networks-on-Chip was held in April 2008 at Newcastle University.

Research has been conducted on integrated optical waveguides and devices comprising an optical network on a chip (ONoC).[8][9]

The possible way to increasing the performance of NoC is use wireless communication channels between

chiplets — named wireless network on chip (WiNoC).[10]

Side benefits

In a multi-core system, connected by NoC, coherency messages and cache miss requests have to pass switches. Accordingly, switches can be augmented with simple tracking and forwarding elements to detect which cache blocks will be requested in the future by which cores. Then, the forwarding elements multicast any requested block to all the cores that may request the block in the future. This mechanism reduces cache miss rate.[11]

Benchmarks

NoC development and studies require comparing different proposals and options. NoC traffic patterns are under development to help such evaluations. Existing NoC benchmarks include NoCBench and MCSL NoC Traffic Patterns.[12]

Interconnect processing unit

An interconnect processing unit (IPU)

which?] in modern heterogeneous applications[definition needed] on a single die
.

See also

Notes

  1. indefinite article corresponding to NoC ("a NoC"). Other sources may pronounce it as /ˌɛnˌoʊˈsiː/ en-oh-SEE
    and therefore use "an NoC".

References

  1. ISBN 978-0-7695-0537-4. Archived
    from the original on 2022-10-22. Retrieved 2022-11-23.
  2. OCLC 326240184.{{cite book}}: CS1 maint: others (link
    )
  3. doi:10.1109/2.976921. Archived
    from the original on 2022-10-22. Retrieved 2022-11-23.
  4. OCLC 895661009
    .
  5. ^ Staff, E. D. N. (2023-07-26). "Network-on-chip (NoC) interconnect topologies explained". EDN. Retrieved 2023-11-17.
  6. ^ "Balancing On-Chip Network Latency in Multi-Application Mapping for Chip-Multiprocessors". IPDPS. May 2014.
  7. ^ NoCS 2007 Archived 2008-09-01 at the Wayback Machine website.
  8. ^ On-Chip Networks Bibliography
  9. ^ "Inter/Intra-Chip Optical Network Bibliography-". Archived from the original on 2015-09-23. Retrieved 2015-07-02.
  10. ^ Slyusar V. I., Slyusar D.V. Pyramidal design of nanoantennas array. // VIII International Conference on Antenna Theory and Techniques (ICATT'11). - Kyiv, Ukraine. - National Technical University of Ukraine "Kyiv Polytechnic Institute". - September 20–23, 2011. - Pp. 140–142. [1] Archived 2019-07-17 at the Wayback Machine
  11. doi:10.1049/iet-cdt.2011.0066
    .
  12. ^ "NoC traffic". www.ece.ust.hk. Archived from the original on 2017-12-25. Retrieved 2018-10-08.
  13. ISBN 978-1-4200-4471-3

Adapted from Avinoam Kolodny's's column in the ACM SIGDA e-newsletter by Igor Markov
The original text can be found at http://www.sigda.org/newsletter/2006/060415.txt

Further reading

External links
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