Instruction unit
The instruction unit (I-unit or IU), also called, e.g., instruction fetch unit (IFU), instruction issue unit (IIU), instruction sequencing unit (ISU), in a central processing unit (CPU) is responsible for organizing program instructions to be fetched from memory, and executed, in an appropriate order, and for forwarding them to an execution unit (E-unit or EU). The I-unit may also do, e.g., address resolution, pre-fetching, prior to forwarding an instruction. It is a part of the control unit, which in turn is part of the CPU.[1]
In the simplest style of
address bus and sent to the memory unit; the memory unit returns the instruction at that address, and it is latched into the instruction register
(IR); and the value of the IP is incremented or over-written by a new value (in the case of a jump or branch instruction), ready for the next instruction cycle.
This becomes a lot more complicated, though, once performance-enhancing features are added, such as
instruction pipelining, out-of-order execution, and even just the introduction of a simple instruction cache.[2]
See also
- Branch predictionand the branch prediction buffer
- Branch target predictor and the branch target buffer
- Branch delay slot
- Instruction scheduling
- Instruction selection
- data hazard
- Scoreboarding
- Very long instruction word (VLIW)
- Superscalarprocessor
- Opcode
- Analysis of Instruction parallelism, Instruction frequencies, Instruction mix
- Instruction path length or Instruction count
References
- ISBN 9781461579571.
- ISBN 1-55860-069-8