Interrupt request

In a

network card

, key presses, or mouse movements.

Interrupt lines are often identified by an index with the format of IRQ followed by a number. For example, on the

PICs, the combined set of lines are referred to as IRQ0 through IRQ15. Technically these lines are named IR0 through IR7, and the lines on the ISA

bus to which they were historically attached are named IRQ0 through IRQ15 (although historically as the number of hardware devices increased, the total possible number of interrupts was increased by means of cascading requests, by making one of the IRQ numbers cascade to another set or sets of numbered IRQs, handled by one or more subsequent controllers).

Newer x86 systems integrate an Advanced Programmable Interrupt Controller (APIC) that conforms to the Intel APIC Architecture. These APICs support a programming interface for up to 255 physical hardware IRQ lines per APIC, with a typical system implementing support for only around 24 total hardware lines.

During the early years of personal computing, IRQ management was often of user concern. With the introduction of plug and play devices this has been alleviated through automatic configuration.^[1]

Overview

When working with personal computer hardware, installing and removing devices, the system relies on interrupt requests. There are default settings that are configured in the system BIOS and recognized by the operating system. These default settings can be altered by advanced users. Modern plug and play technology has not only reduced the need for concern for these settings, but has also virtually eliminated manual configuration.

x86 IRQs

Early PCs using the Intel 8086/8088 processors only had a single PIC, and are therefore limited to eight interrupts. This was expanded to two PICs with the introduction of the 286 based PCs.

Typically, on systems using the Intel 8259 PIC, 16 IRQs are used. IRQs 0 to 7 are managed by one Intel 8259 PIC, and IRQs 8 to 15 by a second Intel 8259 PIC. The first PIC, the master, is the only one that directly signals the CPU. The second PIC, the slave, instead signals to the master on its IRQ 2 line, and the master passes the signal on to the CPU. There are therefore only 15 interrupt request lines available for hardware.

On APIC with

Windows 95 OSR2 may use PIR table to process PCI IRQ steering;^[2]^[3] later, the PIR table has been superseded by ACPI. On APIC with MSI systems, typically there are 224 interrupts available.^[4]

The easiest way of viewing this information on Windows is to use Device Manager or System Information (msinfo32.exe). On Linux, IRQ mappings can be viewed by executing cat /proc/interrupts or using the procinfo utility.

Master PIC

IRQ 0 – system timer (cannot be changed)
IRQ 1 – keyboard on PS/2 port (cannot be changed)
IRQ 2 – cascaded signals from IRQs 8–15 (any devices configured to use IRQ 2 will actually be using IRQ 9)
IRQ 3 –
controller for serial port
2 (shared with serial port 4, if present)

IRQ 4 – serial port controller for serial port 1 (shared with serial port 3, if present)

IRQ 5 – parallel port 3 or sound card
IRQ 6 –
floppy disk controller
IRQ 7 – parallel port 1 (shared with parallel port 2, if present). It is used for printers or for any parallel port if a printer is not present. It can also be potentially be shared with a secondary sound card with careful management of the port.

Slave PIC

IRQ 8 – real-time clock (RTC)
IRQ 9 –
Advanced Configuration and Power Interface (ACPI) system control interrupt on Intel chipsets.^[5]
Other chipset manufacturers might use another interrupt for this purpose, or make it available for the use of peripherals (any devices configured to use IRQ 2 will actually be using IRQ 9)

IRQ 10 – The Interrupt is left open for the use of peripherals (open interrupt/available, SCSI or

NIC

)

IRQ 11 – The Interrupt is left open for the use of peripherals (open interrupt/available, SCSI or NIC)

IRQ 12 – mouse on PS/2 port
IRQ 13 – CPU
floating point unit or inter-processor interrupt
(use depends on OS)

IRQ 14 – primary

CD drives

)

IRQ 15 – secondary ATA channel

Conflicts

In early IBM-compatible

Programmable Interrupt Controller (PIC). The PIC expects interrupt requests from only one device per line, thus more than one device sending IRQ signals along the same line will generally cause an IRQ conflict that can freeze a computer

.

For example, if a

ACPI system control interrupt (SCI is hardwired to IRQ9 on Intel chipsets);^[5] this means ISA MPU-401

cards with a hardwired IRQ 2/9, and MPU-401 device drivers with a hardcoded IRQ 2/9, cannot be used in interrupt-driven mode on a system with ACPI enabled.

In some conditions, two

PCI bus allows for IRQ sharing. PCI Express does not have physical interrupt lines, and uses Message Signaled Interrupts (MSI) to the operating systems

if available.