x86
Designer | AVX512 |
---|
x86 (also known as 80x86
The term is not synonymous with
As of June 2022[update], most
Overview
In the 1980s and early 1990s, when the
A few years after the introduction of the 8086 and 8088, Intel added some complexity to its naming scheme and terminology as the "iAPX" of the ambitious but ill-fated
Although the 8086 was primarily developed for
Modern x86 is relatively uncommon in
There have been several attempts, including by Intel, to end the market dominance of the "inelegant" x86 architecture designed directly from the first simple 8-bit microprocessors. Examples of this are the
Chronology
This article needs additional citations for verification. (March 2020) |
The table below lists processor models and model series implementing various architectures in the x86 family, in chronological order. Each line item is characterized by significantly improved or commercially successful processor microarchitecture designs.
Era | Introduction | Prominent CPU models | Address space | Notable features | |||
---|---|---|---|---|---|---|---|
Linear
|
Virtual | Physical | |||||
x86-16 | 1st | 1978 | Intel 8086, Intel 8088 (1979) | 16-bit | NA | 20-bit | IBM PC/XT (8088)
|
1982 | Intel 80188 /V30 (1983)NEC V20 |
8086-2 ISA, embedded (80186/80188) | |||||
2nd | Intel 80286 and clones | 30-bit | 24-bit | IBM PC/AT
| |||
IA-32 | 3rd | 1985 | AMD Am386 (1991) |
32-bit | 46-bit | 32-bit | IBM PS/2
|
4th (pipelining, cache) | 1989 | Am5x86 (1995) |
pipelining, on-die x87 FPU (486DX), on-die cache | ||||
5th ( Superscalar ) |
1993 | Intel Pentium MMX (1996) |
|||||
1994 | NexGen Nx586 AMD 5k86/K5 (1996) |
Discrete microarchitecture (µ-op translation) | |||||
1995 | MII (1998) |
dynamic execution
| |||||
6th (PAE, µ-op translation) |
1995 | Intel Pentium Pro | 36-bit (PAE) | µ-op translation, conditional move instructions, L2 cache
| |||
1997 | Intel Pentium II, Pentium III (1999) Celeron (1998), Xeon (1998) |
on-package (Pentium II) or on-die (Celeron) L2 Cache, SSE (Pentium III), Slot 1, Socket 370 or Slot 2 (Xeon) | |||||
1997 | AMD K6/K6-2 (1998)/K6-III (1999) | 32-bit | 3DNow!, 3-level cache system (K6-III) | ||||
Enhanced Platform | 1999 | AMD (2004) | 36-bit | MMX+, 3DNow!+, double-pumped bus, Slot A or Socket A | |||
2000 | Transmeta Crusoe | 32-bit | CMS powered x86 platform processor, VLIW -128 core, on-die memory controller, on-die PCI bridge logic
| ||||
Intel Pentium 4 | 36-bit | HTT (Northwood), NetBurst, quad-pumped bus, Trace Cache, Socket 478
| |||||
2003 | Intel Pentium M Intel Core (2006) Pentium Dual-Core (2007) |
XD bit (Dothan) (Intel Core "Yonah")
| |||||
Transmeta Efficeon | HT
| ||||||
IA-64 | 64-bit Transition 1999–2005 |
2001 | Intel Itanium (2001–2017) | 52-bit | 64-bit EPIC architecture, 128-bit VLIW instruction bundle, on-die hardware IA-32 H/W enabling x86 OSes & x86 applications (early generations), software IA-32 EL enabling x86 applications (Itanium 2), Itanium register files are remapped to x86 registers | ||
x86-64 | 64-bit Extended since 2001 |
x86-64 is the 64-bit extended architecture of x86, its Legacy Mode preserves the entire and unaltered x86 architecture. The native architecture of x86-64 processors: residing in the 64-bit Mode, lacks of access mode in segmentation, presenting 64-bit architectural-permit linear address space; an adapted IA-32 architecture residing in the Compatibility Mode alongside 64-bit Mode is provided to support most x86 applications | |||||
2003 | X2 (2006) |
40-bit | |||||
2004 | Celeron D, Pentium D (2005) |
36-bit | Intel VT(Pentium 4 6x2), socket LGA 775
| ||||
2006 | Celeron Dual-Core (2008) |
on-chip quad-core(Core 2 Quad), Smart Shared L2 Cache (Intel Core 2 "Merom") | |||||
2007 | Athlon II (2009) (2009)Turion II |
48-bit | Monolithic quad-core (X4)/triple-core (X3), AM3
| ||||
2008 | Intel Core 2 (45 nm) | 40-bit | SSE4.1
| ||||
Intel Atom | netbook or low power smart device processor, P54C core reused | ||||||
Intel Core i3 (2010) |
QuickPath, on-chip GMCH (Clarkdale), SSE4.2, Extended Page Tables (EPT) for virtualization, macro-op fusion in 64-bit mode,[15][16] (Intel Xeon "Bloomfield" with Nehalem microarchitecture) | ||||||
VIA Nano | hardware-based encryption; adaptive power management | ||||||
2010 | AMD FX | 48-bit | octa-core, CMT(Clustered Multi-Thread), FMA, OpenCL, AM3+ | ||||
2011 | AMD APU A and E Series ( Llano ) |
40-bit | on-die GPGPU, PCI Express 2.0, Socket FM1 | ||||
AMD APU C, E and Z Series ( Bobcat ) |
36-bit | low power smart device APU | |||||
Sandy Bridge/Ivy Bridge ) |
Internal Ring connection, decoded µ-op cache, LGA 1155 socket | ||||||
2012 | AMD APU A Series ( Bulldozer, Trinity and later) |
48-bit | AVX, Bulldozer based APU, Socket FM2 or Socket FM2+ | ||||
Intel Xeon Phi (Knights Corner) | PCI-E add-on card coprocessor for XEON based system, Manycore Chip, In-order P54C , very wide VPU (512-bit SSE), LRBni instructions (8× 64-bit)
| ||||||
2013 | AMD Jaguar (Athlon, Sempron) |
SoC, game console and low power smart device processor | |||||
Intel Silvermont (Atom, Celeron, Pentium) |
36-bit | SoC, low/ultra-low power smart device processor | |||||
) | 39-bit | BMI1, and BMI2 instructions, LGA 1150 socket
| |||||
2015 | Intel ) | SoC, on-chip Broadwell-U PCH-LP (Multi-chip module) | |||||
2015–2020 | Intel Core i9 ) |
46-bit | AVX-512 (restricted to Cannon Lake-U and workstation/server variants of Skylake) | ||||
2016 | Intel Xeon Phi (Knights Landing) | 48-bit | Manycore CPU and coprocessor for Xeon systems, Airmont (Atom) based core | ||||
2016 | AMD Bristol Ridge (AMD (Pro) A6/A8/A10/A12) |
Integrated FCH on die, SoC, AM4 socket | |||||
2017 | AMD Ryzen Series/AMD Epyc Series | AMD's implementation of SMT, on-chip multiple dies | |||||
2017 | Zhaoxin WuDaoKou (KX-5000, KH-20000) | Zhaoxin's first brand new x86-64 architecture | |||||
2018–2021 | Intel Sunny Cove (Ice Lake-U and Y), Cypress Cove (Rocket Lake) | 57-bit | Intel's first implementation of AVX-512 for the consumer segment. Addition of Vector Neural Network Instructions (VNNI) | ||||
2020 | Intel Willow Cove (Tiger Lake-Y/U/H) | Dual ring interconnect architecture, updated Gaussian Neural Accelerator (GNA2), new AVX-512 Vector Intersection Instructions, addition of Control-Flow Enforcement Technology (CET) | |||||
2021 | Intel Alder Lake |
Hybrid design with performance (Golden Cove) and efficiency cores (Gracemont), support for PCIe Gen5 and DDR5, updated Gaussian Neural Accelerator (GNA3) | |||||
Era | Introduction | Prominent CPU models | Address space | Notable features |
History
Designers and manufacturers
At various times, companies such as
Such x86 implementations were seldom simple copies but often employed different internal microarchitectures and different solutions at the electronic and physical levels. Quite naturally, early compatible microprocessors were 16-bit, while 32-bit designs were developed much later. For the personal computer market, real quantities started to appear around 1990 with i386 and i486 compatible processors, often named similarly to Intel's original chips.
After the fully
AMD meanwhile designed and manufactured the advanced but delayed
Some early versions of these microprocessors had heat dissipation problems. The 6x86 was also affected by a few minor compatibility problems, the
Customer ignorance of alternatives to the Pentium series further contributed to these designs being comparatively unsuccessful, despite the fact that the
There were also other contenders, such as
Many additions and extensions have been added to the original x86 instruction set over the years, almost consistently with full backward compatibility.[k] The architecture family has been implemented in processors from Intel, Cyrix, AMD, VIA Technologies and many other companies; there are also open implementations, such as the Zet SoC platform (currently inactive).[17] Nevertheless, of those, only Intel, AMD, VIA Technologies, and DM&P Electronics hold x86 architectural licenses, and from these, only the first two actively produce modern 64-bit designs, leading to what has been called a "duopoly" of Intel and AMD in x86 processors.
However, in 2014 the Shanghai-based Chinese company Zhaoxin, a joint venture between a Chinese company and VIA Technologies, began designing VIA based x86 processors for desktops and laptops. The release of its newest "7" family[18] of x86 processors (e.g. KX-7000), which are not quite as fast as AMD or Intel chips but are still state of the art,[19] had been planned for 2021; as of March 2022 the release had not taken place, however.[20]
From 16-bit and 32-bit to 64-bit architecture
The instruction set architecture has twice been extended to a larger word size. In 1985, Intel released the 32-bit 80386 (later known as i386) which gradually replaced the earlier 16-bit chips in computers (although typically not in embedded systems) during the following years; this extended programming model was originally referred to as the i386 architecture (like its first implementation) but Intel later dubbed it IA-32 when introducing its (unrelated) IA-64 architecture.
In 1999–2003,
In 2023, Intel proposed a major change to the architecture referred to as
Basic properties of the architecture
The x86 architecture is a variable instruction length, primarily "
To further conserve encoding space, most registers are expressed in opcodes using three or four bits, the latter via an opcode prefix in 64-bit mode, while at most one operand to an instruction can be a memory location.[m] However, this memory operand may also be the destination (or a combined source and destination), while the other operand, the source, can be either register or immediate. Among other factors, this contributes to a code size that rivals eight-bit machines and enables efficient use of instruction cache memory. The relatively small number of general registers (also inherited from its 8-bit ancestors) has made register-relative addressing (using small immediate offsets) an important method of accessing operands, especially on the stack. Much work has therefore been invested in making such accesses as fast as register accesses—i.e., a one cycle instruction throughput, in most circumstances where the accessed data is available in the top-level cache.
Floating point and SIMD
A dedicated
The presence of wide SIMD registers means that existing x86 processors can load or store up to 128 bits of memory data in a single instruction and also perform bitwise operations (although not integer arithmetic[n]) on full 128-bits quantities in parallel. Intel's Sandy Bridge processors added the Advanced Vector Extensions (AVX) instructions, widening the SIMD registers to 256 bits. The Intel Initial Many Core Instructions implemented by the Knights Corner Xeon Phi processors, and the AVX-512 instructions implemented by the Knights Landing Xeon Phi processors and by Skylake-X processors, use 512-bit wide SIMD registers.
Current implementations
During
When introduced, in the mid-1990s, this method was sometimes referred to as a "RISC core" or as "RISC translation", partly for marketing reasons, but also because these micro-operations share some properties with certain types of RISC instructions. However, traditional microcode (used since the 1950s) also inherently shares many of the same properties; the new method differs mainly in that the translation to micro-operations now occurs asynchronously. Not having to synchronize the execution units with the decode steps opens up possibilities for more analysis of the (buffered) code stream, and therefore permits detection of operations that can be performed in parallel, simultaneously feeding more than one execution unit.
The latest processors also do the opposite when appropriate; they combine certain x86 sequences (such as a compare followed by a conditional jump) into a more complex micro-op which fits the execution model better and thus can be executed faster or with fewer machine resources involved.
Another way to try to improve performance is to cache the decoded micro-operations, so the processor can directly access the decoded micro-operations from a special cache, instead of decoding them again. Intel followed this approach with the Execution Trace Cache feature in their NetBurst microarchitecture (for Pentium 4 processors) and later in the Decoded Stream Buffer (for Core-branded processors since Sandy Bridge).[25]
Addressing modes
Addressing modes for 16-bit processor modes can be summarized by the formula:[26][27]
Addressing modes for 32-bit x86 processor modes[28] can be summarized by the formula:[29]
Addressing modes for the 64-bit processor mode can be summarized by the formula:[29]
Instruction relative addressing in 64-bit code (RIP + displacement, where RIP is the
The 8086 had 64 KB of eight-bit (or alternatively 32 K-word of 16-bit)
x86 registers
16-bit
The original
One of four possible 'segment registers' (CS, DS, SS and ES) is used to form a memory address. In the original 8086 / 8088 / 80186 / 80188 every address was built from a segment register and one of the general purpose registers. For example ds:si is the notation for an address formed as [16 * ds + si] to allow 20-bit addressing rather than 16 bits, although this changed in later processors. At that time only certain combinations were supported.
The
The
The 8086, 8088, 80186, and 80188 can use an optional floating-point coprocessor, the 8087. The 8087 appears to the programmer as part of the CPU and adds eight 80-bit wide registers, st(0) to st(7), each of which can hold numeric data in one of seven formats: 32-, 64-, or 80-bit floating point, 16-, 32-, or 64-bit (binary) integer, and 80-bit packed decimal integer.[10]: S-6, S-13..S-15 It also has its own 16-bit status register accessible through the fstsw instruction, and it is common to simply use some of its bits for branching by copying it into the normal FLAGS.[32]
In the
32-bit
With the advent of the 32-bit
Two new segment registers (FS and GS) were added. With a greater number of registers, instructions and operands, the machine code format was expanded. To provide backward compatibility, segments with executable code can be marked as containing either 16-bit or 32-bit instructions. Special prefixes allow inclusion of 32-bit instructions in a 16-bit segment or vice versa.
The 80386 had an optional floating-point coprocessor, the
The
64-bit
Starting with the
128-bit
SIMD registers XMM0–XMM15 (XMM0–XMM31 when AVX-512 is supported).
256-bit
SIMD registers YMM0–YMM15 (YMM0–YMM31 when AVX-512 is supported). Lower half of each of the YMM registers maps onto the corresponding XMM register.
512-bit
SIMD registers ZMM0–ZMM31. Lower half of each of the ZMM registers maps onto the corresponding YMM register.
Miscellaneous/special purpose
x86 processors that have a protected mode, i.e. the 80286 and later processors, also have three descriptor registers (GDTR, LDTR, IDTR) and a task register (TR).
32-bit x86 processors (starting with the 80386) also include various special/miscellaneous registers such as
AVX-512 has eight extra 64-bit mask registers K0–K7 for selecting elements in a vector register. Depending on the vector register and element widths, only a subset of bits of the mask register may be used by a given instruction.
Purpose
Although the main registers (with the exception of the instruction pointer) are "general-purpose" in the 32-bit and 64-bit versions of the instruction set and can be used for anything, it was originally envisioned that they be used for the following purposes:
- AL/AH/AX/EAX/RAX: Accumulator
- CL/CH/CX/ECX/RCX: Counter (for use with loops and strings)
- DL/DH/DX/EDX/RDX: Extend the precision of the accumulator (e.g. combine 32-bit EAX and EDX for 64-bit integer operations in 32-bit code)
- BL/BH/BX/EBX/RBX: Base index (for use with arrays)
- SP/ESP/RSP: Stack pointer for top address of the stack.
- BP/EBP/RBP: Stack base pointer for holding the address of the current stack frame.
- SI/ESI/RSI: Source index for string operations.
- DI/EDI/RDI: Destination index for string operations.
- IP/EIP/RIP: Instruction pointer. Holds the program counter, the address of next instruction.
Segment registers:
- CS: Code
- DS: Data
- SS: Stack
- ES: Extra data
- FS: Extra data #2
- GS: Extra data #3
No particular purposes were envisioned for the other 8 registers available only in 64-bit mode.
Some instructions compile and execute more efficiently when using these registers for their designed purpose. For example, using AL as an accumulator and adding an immediate byte value to it produces the efficient add to AL opcode of 04h, whilst using the BL register produces the generic and longer add to register opcode of 80C3h. Another example is double precision division and multiplication that works specifically with the AX and DX registers.
Modern compilers benefited from the introduction of the sib byte (scale-index-base byte) that allows registers to be treated uniformly (minicomputer-like). However, using the sib byte universally is non-optimal, as it produces longer encodings than only using it selectively when necessary. (The main benefit of the sib byte is the orthogonality and more powerful addressing modes it provides, which make it possible to save instructions and the use of registers for address calculations such as scaling an index.) Some special instructions lost priority in the hardware design and became slower than equivalent small code sequences. A notable example is the LODSW instruction.
Structure
64 | 56 | 48 | 40 | 32 | 24 | 16 | 8 |
---|---|---|---|---|---|---|---|
R?X | |||||||
E?X | |||||||
?X | |||||||
?H | ?L |
64 | 56 | 48 | 40 | 32 | 24 | 16 | 8 |
---|---|---|---|---|---|---|---|
? | |||||||
?D | |||||||
?W | |||||||
?B |
16 | 8 |
---|---|
?S |
64 | 56 | 48 | 40 | 32 | 24 | 16 | 8 |
---|---|---|---|---|---|---|---|
R?P | |||||||
E?P | |||||||
?P | |||||||
?PL |
Note: The ?PL registers are only available in 64-bit mode.
64 | 56 | 48 | 40 | 32 | 24 | 16 | 8 |
---|---|---|---|---|---|---|---|
R?I | |||||||
E?I | |||||||
?I | |||||||
?IL |
Note: The ?IL registers are only available in 64-bit mode.
64 | 56 | 48 | 40 | 32 | 24 | 16 | 8 |
---|---|---|---|---|---|---|---|
RIP | |||||||
EIP | |||||||
IP |
Operating modes
Real mode
This section needs additional citations for verification. (January 2014) |
Real Address mode,
In order to use more than 64 KB of memory, the segment registers must be used. This created great complications for compiler implementors who introduced odd pointer modes such as "near", "far" and "huge" to leverage the implicit nature of segmented architecture to different degrees, with some pointers containing 16-bit offsets within implied segments and other pointers containing segment addresses and offsets within segments. It is technically possible to use up to 256 KB of memory for code and data, with up to 64 KB for code, by setting all four segment registers once and then only using 16-bit offsets (optionally with default-segment override prefixes) to address memory, but this puts substantial restrictions on the way data can be addressed and memory operands can be combined, and it violates the architectural intent of the Intel designers, which is for separate data items (e.g. arrays, structures, code units) to be contained in separate segments and addressed by their own segment addresses, in new programs that are not ported from earlier 8-bit processors with 16-bit address spaces.
Unreal mode
Unreal mode is used by some 16-bit
System Management Mode
The System Management Mode (SMM) is only used by the system firmware (BIOS/UEFI), not by operating systems and applications software. The SMM code is running in SMRAM.
Protected mode
This section needs additional citations for verification. (January 2014) |
In addition to real mode, the Intel 80286 supports protected mode, expanding addressable
Each time a segment register is loaded in protected mode, the 80286 must read a 6-byte segment descriptor from memory into a set of hidden internal registers. Thus, loading segment registers is much slower in protected mode than in real mode, and changing segments very frequently is to be avoided. Actual memory operations using protected mode segments are not slowed much because the 80286 and later have hardware to check the offset against the segment limit in parallel with instruction execution.
The
Paging is used extensively by modern multitasking operating systems. Linux, 386BSD and Windows NT were developed for the 386 because it was the first Intel architecture CPU to support paging and 32-bit segment offsets. The 386 architecture became the basis of all further development in the x86 series.
x86 processors that support protected mode boot into real mode for backward compatibility with the older 8086 class of processors. Upon power-on (a.k.a. booting), the processor initializes in real mode, and then begins executing instructions. Operating system boot code, which might be stored in read-only memory, may place the processor into the protected mode to enable paging and other features. Conversely, segment arithmetic, a common practice in real mode code, is not allowed in protected mode.
Virtual 8086 mode
There is also a sub-mode of operation in 32-bit protected mode (a.k.a. 80386 protected mode) called virtual 8086 mode, also known as V86 mode. This is basically a special hybrid operating mode that allows real mode programs and operating systems to run while under the control of a protected mode supervisor operating system. This allows for a great deal of flexibility in running both protected mode programs and real mode programs simultaneously. This mode is exclusively available for the 32-bit version of protected mode; it does not exist in the 16-bit version of protected mode, or in long mode.
Long mode
In the mid 1990s, it was obvious that the 32-bit address space of the x86 architecture was limiting its performance in applications requiring large data sets. A 32-bit address space would allow the processor to directly address only 4 GB of data, a size surpassed by applications such as
In 1999, AMD published a (nearly) complete specification for a 64-bit extension of the x86 architecture which they called x86-64 with claimed intentions to produce. That design is currently used in almost all x86 processors, with some exceptions intended for embedded systems.
Mass-produced x86-64 chips for the general market were available four years later, in 2003, after the time was spent for working prototypes to be tested and refined; about the same time, the initial name x86-64 was changed to AMD64. The success of the AMD64 line of processors coupled with lukewarm reception of the IA-64 architecture forced Intel to release its own implementation of the AMD64 instruction set. Intel had previously implemented support for AMD64[39] but opted not to enable it in hopes that AMD would not bring AMD64 to market before Itanium's new IA-64 instruction set was widely adopted. It branded its implementation of AMD64 as EM64T, and later rebranded it Intel 64.
In its literature and product version names, Microsoft and Sun refer to AMD64/Intel 64 collectively as x64 in the Windows and
Long mode is mostly an extension of the 32-bit instruction set, but unlike the 16–to–32-bit transition, many instructions were dropped in the 64-bit mode. This does not affect actual binary backward compatibility (which would execute legacy code in other modes that retain support for those instructions), but it changes the way assembler and compilers for new code have to work.
This was the first time that a major extension of the x86 architecture was initiated and originated by a manufacturer other than Intel. It was also the first time that Intel accepted technology of this nature from an outside source.
Extensions
Floating-point unit
Early x86 processors could be extended with
Each x87 register, known as ST(0) through ST(7), is 80 bits wide and stores numbers in the
The operations include arithmetic and transcendental functions, including trigonometric and exponential functions, and instructions that load common constants (such as 0; 1; e, the base of the natural logarithm; log2(10); and log10(2)) into one of the stack registers. While the integer ability is often overlooked, the x87 can operate on larger integers with a single instruction than the 8086, 80286, 80386, or any x86 CPU without to 64-bit extensions can, and repeated integer calculations even on small values (e.g., 16-bit) can be accelerated by executing integer instructions on the x86 CPU and the x87 in parallel. (The x86 CPU keeps running while the x87 coprocessor calculates, and the x87 sets a signal to the x86 when it is finished or interrupts the x86 if it needs attention because of an error.)
MMX
MMX is a
MMX added 8 new registers to the architecture, known as MM0 through MM7 (henceforth referred to as MMn). In reality, these new registers were just aliases for the existing x87 FPU stack registers. Hence, anything that was done to the floating-point stack would also affect the MMX registers. Unlike the FP stack, these MMn registers were fixed, not relative, and therefore they were randomly accessible. The instruction set did not adopt the stack-like semantics so that existing operating systems could still correctly save and restore the register state when multitasking without modifications.[40]
Each of the MMn registers are 64-bit integers. However, one of the main concepts of the MMX instruction set is the concept of packed data types, which means instead of using the whole register for a single 64-bit integer (
3DNow!
In 1997, AMD introduced 3DNow!.
3DNow! was designed to be the natural evolution of MMX from integers to floating point. As such, it uses exactly the same register naming convention as MMX, that is MM0 through MM7.[44] The only difference is that instead of packing integers into these registers, two single-precision floating-point numbers are packed into each register. The advantage of aliasing the FPU registers is that the same instruction and data structures used to save the state of the FPU registers can also be used to save 3DNow! register states. Thus no special modifications are required to be made to operating systems which would otherwise not know about them.[45]
SSE and AVX
In 1999, Intel introduced the Streaming SIMD Extensions (SSE)
SSE discarded all legacy connections to the FPU stack. This also meant that this instruction set discarded all legacy connections to previous generations of SIMD instruction sets like MMX. But it freed the designers up, allowing them to use larger registers, not limited by the size of the FPU registers. The designers created eight 128-bit registers, named XMM0 through XMM7. (In AMD64, the number of SSE XMM registers has been increased from 8 to 16.) However, the downside was that operating systems had to have an awareness of this new set of instructions in order to be able to save their register states. So Intel created a slightly modified version of Protected mode, called Enhanced mode which enables the usage of SSE instructions, whereas they stay disabled in regular Protected mode. An OS that is aware of SSE will activate Enhanced mode, whereas an unaware OS will only enter into traditional Protected mode.
SSE is a SIMD instruction set that works only on floating-point values, like 3DNow!. However, unlike 3DNow! it severs all legacy connection to the FPU stack. Because it has larger registers than 3DNow!, SSE can pack twice the number of
The Advanced Vector Extensions (AVX) doubled the size of SSE registers to 256-bit YMM registers. It also introduced the VEX coding scheme to accommodate the larger registers, plus a few instructions to permute elements. AVX2 did not introduce extra registers, but was notable for the addition for masking,
AVX-512 features yet another expansion to 32 512-bit ZMM registers and a new EVEX scheme. Unlike its predecessors featuring a monolithic extension, it is divided into many subsets that specific models of CPUs can choose to implement.
Physical Address Extension (PAE)
Physical Address Extension or PAE was first added in the Intel Pentium Pro, and later by AMD in the Athlon processors,[47] to allow up to 64 GB of RAM to be addressed. Without PAE, physical RAM in 32-bit protected mode is usually limited to 4 GB. PAE defines a different page table structure with wider page table entries and a third level of page table, allowing additional bits of physical address. Although the initial implementations on 32-bit processors theoretically supported up to 64 GB of RAM, chipset and other platform limitations often restricted what could actually be used. x86-64 processors define page table structures that theoretically allow up to 52 bits of physical address, although again, chipset and other platform concerns (like the number of DIMM slots available, and the maximum RAM possible per DIMM) prevent such a large physical address space to be realized. On x86-64 processors PAE mode must be active before the switch to long mode, and must remain active while long mode is active, so while in long mode there is no "non-PAE" mode. PAE mode does not affect the width of linear or virtual addresses.
x86-64
This section needs additional citations for verification. (March 2016) |
By the 2000s, 32-bit x86 processors' limits in memory addressing were an obstacle to their use in high-performance computing clusters and powerful desktop workstations. The aged 32-bit x86 was competing with much more advanced 64-bit RISC architectures which could address much more memory. Intel and the whole x86 ecosystem needed 64-bit memory addressing if x86 was to survive the 64-bit computing era, as workstation and desktop software applications were soon to start hitting the limits of 32-bit memory addressing. However, Intel felt that it was the right time to make a bold step and use the transition to 64-bit desktop computers for a transition away from the x86 architecture in general, an experiment which ultimately failed.
In 2001, Intel attempted to introduce a non-x86 64-bit architecture named IA-64 in its Itanium processor, initially aiming for the high-performance computing market, hoping that it would eventually replace the 32-bit x86.[48] While IA-64 was incompatible with x86, the Itanium processor did provide emulation abilities for translating x86 instructions into IA-64, but this affected the performance of x86 programs so badly that it was rarely, if ever, actually useful to the users: programmers should rewrite x86 programs for the IA-64 architecture or their performance on Itanium would be orders of magnitude worse than on a true x86 processor. The market rejected the Itanium processor since it broke backward compatibility and preferred to continue using x86 chips, and very few programs were rewritten for IA-64.
AMD decided to take another path toward 64-bit memory addressing, making sure backward compatibility would not suffer. In April 2003, AMD released the first x86 processor with 64-bit general-purpose registers, the Opteron, capable of addressing much more than 4 GB of virtual memory using the new x86-64 extension (also known as AMD64 or x64). The 64-bit extensions to the x86 architecture were enabled only in the newly introduced long mode, therefore 32-bit and 16-bit applications and operating systems could simply continue using an AMD64 processor in protected or other modes, without even the slightest sacrifice of performance[49] and with full compatibility back to the original instructions of the 16-bit Intel 8086.[50]: 13–14 The market responded positively, adopting the 64-bit AMD processors for both high-performance applications and business or home computers.
Seeing the market rejecting the incompatible Itanium processor and Microsoft supporting AMD64, Intel had to respond and introduced its own x86-64 processor, the Prescott Pentium 4, in July 2004.[51] As a result, the Itanium processor with its IA-64 instruction set is rarely used and x86, through its x86-64 incarnation, is still the dominant CPU architecture in non-embedded computers.
x86-64 also introduced the
As a result of AMD's 64-bit contribution to the x86 lineage and its subsequent acceptance by Intel, the 64-bit RISC architectures ceased to be a threat to the x86 ecosystem and almost disappeared from the workstation market. x86-64 began to be utilized in powerful
Virtualization
Prior to 2005, x86 architecture processors were unable to meet the
.The introduction of the AMD-V and Intel VT-x instruction sets in 2005 allowed x86 processors to meet the Popek and Goldberg virtualization requirements.[52]
AES
APX (Advanced Performance Extensions)
APX (Advanced Performance Extensions) are extensions to double the number of general-purpose registers from 16 to 32 and add new features to improve general-purpose performance.[53][54][55][56] These extensions have been called "generational"[57] and "the biggest x86 addition since 64 bits".[58] Intel contributed APX support to GNU Compiler Collection (GCC) 14.[59]
According to the architecture specification,[60] the main features of APX are:
- 16 additional general-purpose registers, called the Extended GPRs (EGPRs)
- Three-operand instruction formats for many integer instructions
- New conditional instructions for loads, stores, and comparisons with common instructions that don't modify flags
- Optimized register save/restore operations
- A 64-bit absolute direct jump instruction
Extended GPRs for general purpose instructions are encoded using 2-byte
See also
- x86 assembly language
- x86 instruction listings
- x86 memory segmentation
- CPUID
- Itanium
- x86-64
- 680x0, a competing architecture in the 16 & early 32bit eras
- PowerPC, a competing architecture in the later 32-bit and 64-bit eras
- Microarchitecture
- List of AMD processors
- List of Intel processors
- List of Intel CPU microarchitectures
- List of VIA microprocessor cores
- List of x86 manufacturers
- Interrupt request
- iAPX
- Transient execution CPU vulnerability
- Tick–tock model
- Virtual legacy wires
Notes
- ^ Unlike the microarchitecture (and specific electronic and physical implementation) used for a specific microprocessor design.
- GRID Compasslaptop, for instance.
- 80286processors.
- 7400 series support components, including multiplexers, buffers, and glue logic.
- ^ The actual meaning of iAPX was Intel Advanced Performance Architecture, or sometimes Intel Advanced Processor Architecture.
- ^ late 1981 to early 1984, approximately
- architectures, which, due to the price sensitivity, low power, and hardware simplicity requirements, outnumber the x86.
- ^ The NEC V20 and V30 also provided the older 8080 instruction set, allowing PCs equipped with these microprocessors to operate CP/M applications at full speed (i.e., without the need to simulate an 8080 by software).
- Fablesscompanies designed the chip and contracted another company to manufacture it, while fabbed companies would do both the design and the manufacturing themselves. Some companies started as fabbed manufacturers and later became fabless designers, one such example being AMD.
- ^ It had a slower FPU however, which is slightly ironic as Cyrix started out as a designer of fast floating-point units for x86 processors.
- P5 Pentiumduring 1993 (as numbers could not be trademarked). However, the term x86 was already established among technicians, compiler writers etc.
- ^ 16-bit and 32-bit microprocessors were introduced during 1978 and 1985 respectively; plans for 64-bit was announced during 1999 and gradually introduced from 2003 and onwards.
- ^ Some "CISC" designs, such as the PDP-11, may use two.
- ^ That is because integer arithmetic generates carry between subsequent bits (unlike simple bitwise operations).
- ^ Two MSRs of particular interest are SYSENTER_EIP_MSR and SYSENTER_ESP_MSR, introduced on the Pentium® II processor, which store the address of the kernel mode system service handler and corresponding kernel stack pointer. Initialized during system startup, SYSENTER_EIP_MSR and SYSENTER_ESP_MSR are used by the SYSENTER (Intel) or SYSCALL (AMD) instructions to achieve Fast System Calls, about three times faster than the software interrupt method used previously.
- ^ Because a segmented address is the sum of a 16-bit segment multiplied by 16 and a 16-bit offset, the maximum address is 1,114,095 (10FFEF hex), for an addressability of 1,114,096 bytes = 1 MB + 65,520 bytes. Before the 80286, x86 CPUs had only 20 physical address lines (address bit signals), so the 21st bit of the address, bit 20, was dropped and addresses past 1 MB were mirrors of the low end of the address space (starting from address zero). Since the 80286, all x86 CPUs have at least 24 physical address lines, and bit 20 of the computed address is brought out onto the address bus in real mode, allowing the CPU to address the full 1,114,096 bytes reachable with an x86 segmented address. On the popular IBM PC platform, switchable hardware to disable the 21st address bit was added to machines with an 80286 or later so that all programs designed for 8088/8086-based models could run, while newer software could take advantage of the "high" memory in real mode and the full 16 MB or larger address space in protected mode—see A20 gate.
- ^ An extra descriptor record at the top of the table is also required, because the table starts at zero but the minimum descriptor index that can be loaded into a segment register is 1; the value 0 is reserved to represent a segment register that points to no segment.
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Further reading
- Rosenblum, Mendel; Garfinkel, Tal (May 2005). "Virtual machine monitors: current technology and future trends". IEEE Computer. 38 (5): 39–47. S2CID 10385623.
External links
- Why Intel can't seem to retire the x86
- 32/64-bit x86 Instruction Reference
- Intel Intrinsics Guide, an interactive reference tool for Intel intrinsic instructions
- Intel® 64 and IA-32 Architectures Software Developer's Manuals
- AMD Developer Guides, Manuals & ISA Documents, AMD64 Architecture