Silicon on insulator

Source: Wikipedia, the free encyclopedia.
For silicon on insulator optical devices, see Silicon photonics.

In

electrical insulator, typically silicon dioxide or sapphire (these types of devices are called silicon on sapphire, or SOS). The choice of insulator depends largely on intended application, with sapphire being used for high-performance radio frequency (RF) and radiation-sensitive applications, and silicon dioxide for diminished short-channel effects in other microelectronics devices.[2] The insulating layer and topmost silicon layer also vary widely with application.[3]

Industry need

SOI technology is one of several manufacturing strategies to allow the continued miniaturization of

bulk CMOS) processing include:[4]

  • Lower parasitic capacitance due to isolation from the bulk silicon, which improves power consumption at matched performance
  • Resistance to
    latchup
    due to complete isolation of the n- and p-well structures
  • Higher performance at equivalent VDD. Can work at low VDDs[5]
  • Reduced temperature dependency due to no doping
  • Better yield due to high density, better wafer utilization
  • Reduced antenna issues
  • No body or well taps are needed
  • Lower leakage currents due to isolation thus higher power efficiency
  • Inherently radiation hardened (resistant to soft errors), reducing the need for redundancy

From a manufacturing perspective, SOI substrates are compatible with most conventional fabrication processes. In general, an SOI-based process may be implemented without special equipment or significant retooling of an existing factory. Among challenges unique to SOI are novel metrology requirements to account for the buried oxide layer and concerns about differential stress in the topmost silicon layer. The threshold voltage of the transistor depends on the history of operation and applied voltage to it, thus making modeling harder. The primary barrier to SOI implementation is the drastic increase in substrate cost, which contributes an estimated 10–15% increase to total manufacturing costs.[6][additional citation(s) needed] FD-SOI (Fully Depleted Silicon On Insulator) has been seen as a potential low cost alternative to FinFETs.[7]

SOI transistors

An SOI MOSFET is a

bulk MOSFET. Obviously there are some advantages over the bulk MOSFETs. The film is very thin in FDSOI devices so that the depletion region covers the whole channel region. In FDSOI the front gate (GOX) supports fewer depletion charges than the bulk so an increase in inversion charges occurs resulting in higher switching speeds. The limitation of the depletion charge by the BOX induces a suppression of the depletion capacitance and therefore a substantial reduction of the subthreshold swing allowing FD SOI MOSFETs to work at lower gate bias resulting in lower power operation. The subthreshold swing can reach the minimum theoretical value for MOSFET at 300K, which is 60mV/decade. This ideal value was first demonstrated using numerical simulation.[12][13] Other drawbacks in bulk MOSFETs, like threshold voltage roll off, etc. are reduced in FDSOI since the source and drain electric fields can't interfere due to the BOX. The main problem in PDSOI is the "floating body effect (FBE)" since the film is not connected to any of the supplies.[citation needed
]

Manufacture of SOI wafers

SIMOX process
Smart Cut process

SiO
2-based SOI wafers can be produced by several methods:

An exhaustive review of these various manufacturing processes may be found in reference[1]

Use in the microelectronics industry

tri-gate transistors to improve transistor performance. In January 2005, Intel researchers reported on an experimental single-chip silicon rib waveguide Raman laser built using SOI.[23]

As for the traditional foundries, in July 2006

Chartered Semiconductor devoted a whole fab to SOI.[25]

Use in high-performance radio frequency (RF) applications

In 1990, Peregrine Semiconductor began development of an SOI process technology utilizing a standard 0.5 μm CMOS node and an enhanced sapphire substrate. Its patented silicon on sapphire (SOS) process is widely used in high-performance RF applications. The intrinsic benefits of the insulating sapphire substrate allow for high isolation, high linearity and electro-static discharge (ESD) tolerance. Multiple other companies have also applied SOI technology to successful RF applications in smartphones and cellular radios.[26][additional citation(s) needed]

Use in photonics

SOI wafers are widely used in silicon photonics.[27] The crystalline silicon layer on insulator can be used to fabricate optical waveguides and other optical devices, either passive or active (e.g. through suitable implantations). The buried insulator enables propagation of infrared light in the silicon layer on the basis of total internal reflection. The top surface of the waveguides can be either left uncovered and exposed to air (e.g. for sensing applications), or covered with a cladding, typically made of silica[28]

Disadvantages

The major disadvantage of SOI technology when compared to conventional semiconductor industry is increased cost of manufacturing.[29] As of 2012 only IBM and AMD used SOI as basis for high-performance processors and the other manufacturers (Intel, TSMC, Global Foundries etc.) used conventional silicon wafers to build their CMOS chips.[29]

SOI market

As of 2020 the market utilizing the SOI process was projected to grow up by ~15% for the next 5 years according to Market Research Future group.[30]

See also

References

  1. ^
    doi:10.1063/1.1558223
    .
  2. ISBN 0-7923-7640-4
    .
  3. ISBN 978-0-7923-9150-0
    .
  4. ^ Mendez, Horacio (April 2009). "Silicon-on-insulator — SOI technology and ecosystem — Emerging SOI applications" (PDF). SOI Industry Consortium.
  5. ^ Kodeti, Narayan M. (October 2010). "Silicon On Insulator (SOI) Implementation" (PDF). White Paper. Infotech. Archived from the original (PDF) on 2013-04-18.
  6. ^ "IBM touts chipmaking technology". cnet.com. 29 March 2001. Retrieved 22 April 2018.
  7. ^ "Samsung, GF Ramp FD-SOI". 27 April 2018.
  8. ^ US 6835633, "SOI wafers with 30-100 Ang. Buried OX created by wafer bonding using 30-100 Ang. thin oxide as bonding layer" 
  9. ^ US 7002214, "Ultra-thin body super-steep retrograde well (SSRW) FET devices" 
  10. S2CID 43561939
    .
  11. ^ US 7138685, "Vertical MOSFET SRAM cell"  describes SOI buried oxide (BOX) structures and methods for implementing enhanced SOI BOX structures
  12. ^ Balestra, F. (1985). Characterization and Simulation of SOI MOSFETs with Back Potential Control (PhD). INP-Grenoble.
  13. ISBN 978-1-119-06922-5
    .
  14. ^ US 5888297, Atsushi Ogura, "Method of fabricating SOI substrate", issued 1999-03-30 
  15. ^ US 5061642, Hiroshi Fujioka, "Method of manufacturing semiconductor on insulator", issued 1991-10-29 
  16. ISBN 978-0-471-57481-1
    .
  17. ^ US 4771016, Bajor, George & et al., "Using a rapid thermal process for manufacturing a wafer bonded soi semiconductor", issued 1988-09-13 
  18. ^ "SIGEN.COM". www.sigen.com. Retrieved 22 April 2018.
  19. ^ Yonehara, T; Sakaguchi, K. "ELTRAN® Novel SOI Wafer Technology" (PDF). Cutting Edge 2. Canon.
  20. ^ US 5417180 
  21. ^ Vries, Hans de. "Chip Architect: Intel and Motorola/AMD's 130 nm processes to be revealed". chip-architect.com. Retrieved 22 April 2018.
  22. ^ "NXP Semiconductors - Automotive, Security, IoT". www.freescale.com. Retrieved 22 April 2018.
  23. S2CID 4423069
    .
  24. ^ "TSMC has no customer demand for SOI technology". Fabtech: The online information source for semiconductor professionals. Archived from the original on 28 September 2007. Retrieved 22 April 2018.
  25. ^ Chartered expands foundry market access to IBM's 90nm SOI technology
  26. ^ Madden, Joe. "Handset RFFEs: MMPAs, Envelope Tracking, Antenna Tuning, FEMs, and MIMO" (PDF). Mobile Experts. Archived from the original (PDF) on 4 March 2016. Retrieved 2 May 2012.
  27. ISBN 978-0-470-87034-1
    . Retrieved 22 April 2018 – via Google Books.
  28. ^ Rigny, Arnaud. "Silicon-on-Insulator Substrates: The Basis of Silicon Photonics". Photonics.com. Retrieved 7 May 2023.
  29. ^ a b McLellan, Paul. "Silicon on Insulator (SOI)". Semiwiki. Retrieved 2021-03-07.
  30. ^ Future, Market Research (2021-02-17). "Silicon on Insulator (SoI) Market is Anticipated to Surpass USD 2.40 Billion By 2026 | APAC Region to Remain Forerunner in Global Silicon on Insulator Industry". GlobeNewswire News Room (Press release). Retrieved 2021-03-07.
  • SOI Industry Consortium - a site with extensive information and education for SOI technology
  • SOI IP portal - A search engine for SOI IP
  • AMDboard - a site with extensive information regarding SOI technology
  • Advanced Substrate News - a newsletter about the SOI industry, produced by Soitec
  • MIGAS '04 - The 7th session of MIGAS International Summer School on Advanced Microelectronics, devoted to SOI technology and devices
  • MIGAS '09 - 12th session of the International Summer School on Advanced Microelectronics: "Silicon on Insulator (SOI) Nanodevices"
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