Talk:USB4

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Is anyone else seeing "[[]][[]][[]]" at the top of the page? I've attached a screenshot. I can't figure out where it's coming from in the source.

TaylorKline (talk) 16:04, 6 January 2021 (UTC)[reply]

It is coming from deprecated/removed parameters in the infobox template (and a bug in wikisource engine). 2A00:1370:812D:F205:B90D:8F1:41E5:3D52 (talk) 12:51, 16 April 2021 (UTC)[reply]

The article doesn't discuss it at all, while USB 3.0's article, for contrast, has a whole section about it. -Cardace (talk) 21:10, 3 June 2021 (UTC)[reply]

Not directly. It is backwared compatible with USB 1.x and 2.0, as it uses dedicated lines in the connector, but the compatibility with 3.x requires extra (possibly optional, but all vendors are likely to implement it by detecting the other side, and switching to USB 3) support, as the USB 3.2 is tunneled in USB4. 81.6.34.63 (talk) 07:32, 1 June 2022 (UTC)[reply]

if USB4 does not directly support USB 3.2 (and 3.X what a naming mess) then this article should have a HUGE HEADLINE saying so. are you sure? 2601:40D:8100:9400:75D2:A01F:5B18:248E (talk) 23:27, 18 January 2023 (UTC)[reply]

The USB-IF announcement hopefully wasn't misleadingly worded. It states: "Key characteristics of the USB4 solution include: ... Backward compatibility with USB 3.2, USB 2.0 and Thunderbolt 3 ... Even as the USB4 specification introduces a new underlying protocol, compatibility with existing USB 3.2, USB 2.0 and Thunderbolt 3 hosts and devices is supported"

https://www.usb.org/sites/default/files/2019-09/USB-IF_USB4%20spec%20announcement_FINAL.pdf 2601:40D:8100:9400:75D2:A01F:5B18:248E (talk) 23:55, 18 January 2023 (UTC)[reply]

it's not clear here whether (or not) USB 3.2 native signals are supported by USB4. native, versus "tunneling". example: if a USB 3.2 2x2 (20Gbps) SSD enclosure is connected to a USB4 controller, will it work? or won't it. 2601:40D:8100:9400:75D2:A01F:5B18:248E (talk) 23:20, 18 January 2023 (UTC)[reply]

I think it must be. 2601:40D:8100:9400:75D2:A01F:5B18:248E (talk) 00:01, 19 January 2023 (UTC)[reply]

The USB-IF announcement hopefully wasn't misleadingly worded. It states: "Key characteristics of the USB4 solution include: ... Backward compatibility with USB 3.2, USB 2.0 and Thunderbolt 3 ... Even as the USB4 specification introduces a new underlying protocol, compatibility with existing USB 3.2, USB 2.0 and Thunderbolt 3 hosts and devices is supported"

https://www.usb.org/sites/default/files/2019-09/USB-IF_USB4%20spec%20announcement_FINAL.pdf 2601:40D:8100:9400:75D2:A01F:5B18:248E (talk) 00:02, 19 January 2023 (UTC)[reply]

I answered my own question. The answer is "yes". Native USB 3.2 (up through 2x2 20Gbps) is preserved with USB4.

Quote from the 2019 USB4 spec:

"When configured over a USB Type-C® connector interface, USB4 functionally replaces USB 3.2

while retaining USB 2.0 bus operating in parallel. Enhanced SuperSpeed USB, as defined in USB

3.2, remains the fundamental architecture for USB data transfer on a USB4 Fabric."

page 10 https://www.usb.org/sites/default/files/USB4%20Specification.zip 2601:40D:8100:9400:AD8F:11DD:575C:16E2 (talk) 12:21, 20 January 2023 (UTC)[reply]

https://en.wikipedia.org/wiki/USB4#Data_transfer_modes

Data transfer modes
[...] "Therefore, when the host and device do not support optional PCIe tunneling, the maximum non-display bandwidth is limited to USB 3.2 20 Gbit/s, while only USB 3.2 10 Gbit/s is mandatory."

above is from the article text. it's getting cited throughout the internet. I believe it's incorrect.
below is from the USB4 spec

section §2.1.1.4.1 USB4 Peripheral Device
A USB4 peripheral device supports 20G USB4 operation (Gen2x2) and optionally 40G USB4 operation (Gen3x2).

section §2.1.1.4.2 USB4 Hub
A USB4 hub supports 20G USB4 operation (Gen2x2) and 40G USB4 operation (Gen3x2).

section §2.1.1.5 USB4 Host
A USB4 host supports 20G USB4 operation (Gen2x2) and optionally 40G USB4 operation (Gen3x2).
2601:40D:8100:9400:C892:CEF6:8C23:551D (talk) 00:05, 12 March 2023 (UTC)[reply]

I think the distinction is that the your underlined 20Gbps speed includes display traffic, while the paragraph you're commenting on is for non display USB3-only traffic. Interestingly, v2.0 spec removed that limitation and now USB3 can optionally utilize the full available bandwidth. I've edited the paragraph to reflect this. Sdht (talk) 18:23, 11 May 2023 (UTC)[reply]

— Preceding unsigned comment added by 2601:40D:8281:E6B0:6024:910B:8AE:E635 (talk) 15:43, 11 November 2023 (UTC)[reply]

Sorry, I don't mean to be argumentative. But I repeat:

Those 3 sections §2.1.1.4 and §2.1.1.5 plainly say native USB 3.2 (Gen2x2) 20Gbps is supported. it is mandatory.

The preceding Architectural Overview - Section 2 and Figures 2-1 explain and illustrate that ALL native USB 3.2 continues to be supported as-is. (as-was). The logical USB4 "Router" block diagram boxes in the Figures 2-1 show this. Each Router contains a "USB3 Adapter" (for tunnel re-packaging USB4 style), and next to it, a separate exterior USB3 straight-thru bypass.  (denoted as Enhanced SuperSpeed).

2.1 USB4 System Description


Figure 2-1 illustrates the dual bus architecture of USB 3.2 as augmented by USB4. As architected, backward compatibility is supported with minimum interoperability starting at USB 2.0, working up through USB 3.2, and finally up to USB4

The USB4 v2 spec adds emphasis that USB 3.2 Enhanced SuperSpeed support exists in the Host, and down,

"Enhanced SuperSpeed" means the modes collectively in USB 3.2 including Gen2x2 20Gbps dual-lane mode over USB-C.

§2.1.1.5 USB4 Host
A USB4 Host contains:
• A Host Router.
• A USB 2.0 Host.
• An Enhanced SuperSpeed Host.
• A DisplayPort Source.

§2.1.1.4.2 USB4 Hub
A USB4 Hub contains:
• A Device Router.
• An Enhanced SuperSpeed USB Hub.
• A PCIe Switch.
• A USB 2.0 Hub.

§2.1.1.4.1 USB4 Peripheral Device
A USB4 Peripheral Device contains a Device Router and can also optionally contain one or more of the following:
• An Enhanced SuperSpeed Function.
• A USB 2.0 Function.
• A PCIe Function.
• A DisplayPort Source or Sink.

The source of 20Gbps confusion and error in this article seems to be due to a mis-reading of Section §9.2.1 which pertains to Tunneled protocol. That entire section falls under the title 9 USB3 Tunneling. Yes, for that situation (tunneling), the USB3 Gen2x2 20Gbps support is relegated to optional. The difficulty with tunneling USB3 Gen2x2 is, the 2 lanes of 10Gbps packets would need to be merged together into single payloads of 20Gbps tunneled packets. (and decoded back to 2 lanes of 10Gbps at the opposite endpoint). USB-IF apparently deemed that to be too grubby to mandate in USB4, and declared it optional.

But un-tunneled native USB3 Gen2x2 20Gbps traffic (and even USB 2) still needs to be supported - per Sections 2 cited above. 2601:40D:8281:E6B0:6024:910B:8AE:E635 (talk) 15:08, 11 November 2023 (UTC)[reply]

USB-IF has released new logos and guidelines to use them: https://www.usb.org/logo-license. The logos in Table "Comparison of transfer modes" needs to be updated. I'm not sure if I need to actually recreate the new logos similar to the current logos, or if I can copy the logos from the USB-IF pdf as "fair use". Sdht (talk) 18:27, 11 May 2023 (UTC)[reply]

a. USB4 Gen 2x1 is different from USB 3.2 Gen 2x2. They only signify the same speed (10 Gbit/s), but are coded differently on the electrical layer.

shouldn't this read as .. USB4 Gen 2x1 is different from USB 3.2 Gen 2x1. They only signify the same speed (10 Gbit/s), but are coded differently on the electrical layer. ..? 2A00:6020:439A:9E00:5155:62C8:DD3E:BAA3 (talk) 15:02, 19 August 2023 (UTC)[reply]

Gen2x2 is 20Gbps, at 10Gbps per lane. 2601:40D:8281:E6B0:9897:E015:EB35:3A98 (talk) 21:19, 10 November 2023 (UTC)[reply]

possibly that "note [a]" intended to say:

a. USB4 Gen 2 is different from USB 3.2 Gen 2. They only signify the same lane speed (10 Gbit/s), but are coded differently on the electrical layer. USB4 Gen2 uses 64b/66b encoding. USB 3.2 Gen2 uses 128b/132b encoding.

• the USB 3.2 spec indicates Gen2 encoding is 128b/132b.

• the USB 4 spec is peppered with notes about Gen2 encoding 64b/66b like this sample:

When RS-FEC is off, Transport Layer Packets are encoded using either 64b/66b encoding (for Gen 2 speed traffic) or 128b/132b encoding (for Gen 3 speed traffic).

(RS-FEC is another encoding option: "Reed-Solomon Forward Error-Correction")

2601:40D:8281:E6B0:F536:34D:84B1:B4D0 (talk) 18:12, 15 November 2023 (UTC)[reply]

the beginning of this article states:
"USB4 is based on the Thunderbolt 3 protocol specification, which Intel has donated to the USB-IF,"

but according to Intel press, the TB spec was contributed to USB-IF.
that's a far cry from "donated".
the TB spec was never published publicly, nor are its full details incorporated into the USB4 spec text.
nor is it available on USB-IF site.
it still requires intel NDA to request it.
https://www.thunderbolttechnology.net/developer-application
https://www.thunderbolttechnology.net/developer-application/new

if a formal "ThunderBolt Protocol Specification" even exists,
what kind of "donated to the USB-IF" is that!?

see https://www.intel.com/content/www/us/en/newsroom/news/intel-leads-industry-next-generation-thunderbolt.html

How Thunderbolt Drives the Industry:
With the vision to make Thunderbolt available to everyone, Intel in 2019 contributed to the USB Promoter Group its Thunderbolt protocol specification, which served as the basis for USB4. As a leader in this industry group, Intel has worked to extend the performance of USB4 to the next level.  2601:40D:8281:E6B0:6024:910B:8AE:E635 (talk) 22:50, 11 November 2023 (UTC)[reply]

Furthermore, to even say ThunderBolt3 served as a basis for USB4 is an Intel self-marketing exaggeration.

Minus public specs, Intel's ThunderBolt4 marketing info admits it delivers no more than 3,000 MB/s tunneled PCIe data.

It attempts to boost perception by saying in the same sentence it connects to PCIe3 x4 lane 32Gbps. (but so what?)

See pg 5 -- https://www.thunderbolttechnology.net/sites/default/files/intel-thunderbolt4-announcement-press-deck.pdf

ThunderBolt's 3000 MB/s is a mere smidgen more than 22Gbps.

USB4 leapfrogged ahead of ThunderBolt, with up to 40Gbps tunneled PCIe data.

math:

22Gbps = 22 x 230 = 22 x 10243 wherein Gbps is binary notation. (Billion = 10003)

divide by 8 for Bytes/sec. divide by 1 million for inflated MB/s decimal notation.

22Gbps = 2953 MB/s

2601:40D:8281:E6B0:C4A2:7CCC:6C3B:F5B4 (talk) 08:01, 12 November 2023 (UTC)[reply]

Yep, I believe this indeed needs a rewording since I never expected Intel to just "donate" some of its tech. It's not like AMD donating Mantle to Vulkan. - Alexceltare2 (talk) 11:31, 14 November 2023 (UTC)[reply]

I don't think this needs an in-depth discussion, I don't think changing "donated" to "contributed" is controversial and is factually accurate, so I've gone ahead and changed it. 1lann (talk) 23:17, 14 November 2023 (UTC)[reply]

This USB4 article begins with a marketing embellishment that promotes Intel's competing ThunderBolt product line.
"USB4 is based on the Thunderbolt 3 protocol specification,..."

Compare to opposite claim in text extracted directly from the USB4 Specification:

2 Architectural Overview
Enhanced SuperSpeed USB, as defined in the USB 3.2 Specification, remains the fundamental architecture for USB data transfer on a USB4 Fabric.

In the hierarchy of the USB4 specification, Thunderbolt 3 compatibility / interoperability is a mere optional consideration that is appended lastly as the final Chapter 13 and expressed as a recipe of patch-ins .

13 Interoperability with Thunderbolt™ 3 (TBT3) Systems
This chapter defines requirements for a USB4 Product to be TBT3-Compatible.

In fact, neither a USB4 Host nor Peripheral Device is required to provide any TB compatibility at all.

2.1.5 Thunderbolt™ 3 (TBT3) Compatibility Support
A USB4 Host or USB4 Peripheral Device can optionally support interoperability with Thunderbolt 3 (TBT3) products.

A USB4 Hub is required to support interoperability with Thunderbolt 3 products on all of its Downstream Facing Ports. A USB4-Based Dock is required to support interoperability with Thunderbolt 3 products on its Upstream Facing Port in addition to all of its Downstream Facing Ports.

So, while some comparable aspects of ThunderBolt (eg PCIe tunneling) were implemented in USB4,
and TB3 compatibility support was mandated for USB4 Hubs/Docks, (read: foisted)
Don't you think this Wikipedia article wording demerits USB4 as a ThunderBolt me-too imitation...
...with gratuitous bias favoring Intel TB marketing narrative.

2601:40D:8281:E6B0:EDB9:254E:30C0:F0A (talk) 08:23, 16 November 2023 (UTC)[reply]

The wording "based" is used by the USB Promoters Group in this announcement: https://usb.org/sites/default/files/2019-02/USB_PG_USB4_DevUpdate_Announcement_FINAL_20190226.pdf

Although I agree it's unclear how much of USB4 is really based on TBT3. 1lann (talk) 10:39, 17 November 2023 (UTC)[reply]

yes, but half of the two co-signers of that press release are Intel

read: foisted

2601:40D:8281:E6B0:864:3360:CA4:294C (talk) 17:50, 17 November 2023 (UTC)[reply]

there are a couple TB3 comments under Hardware Support that seem off-topic there.
wouldn't they be best located under the dedicated Thunderbolt 3 compatibility section?
they seem to serve no purpose except promo plugs for TB3 where they're presently at.

(talk) 07:14, 18 November 2023 (UTC)[reply]

meanwhile, I edited-in some touch-ups in its statements and their order, to make it more balanced and cohesive.

note. that cited [Brad Saunders quote] and article containing it is duplicated (plagiarized) throughout the internet, no telling where it began, with no link to the original published article, nor more importantly, a link to that actual quotation source.

maybe it should instead say  "Brad Saunders is rumored to have said [....]"

for example, google: “We do expect PC vendors to broadly support Thunderbolt backward compatibility, because most of what they need is already built into the USB 4 design,”

2601:40D:8281:E6B0:1956:C17C:AD27:3C94 (talk) 17:37, 18 November 2023 (UTC)[reply]

The article has been fully protected for 3 days due to edit warring. Please try to resolve the content dispute here on the talk page. If the involved editors are unable to achieve consensus, please make use of

Daniel Quinlan, There is no content dispute here. There is one IP editor editing in violation of policies and editing guidelines, and others trying to restrain them. Characterising this as "edit war" and applying full protection is way over the top, and should not be labelled as "Requested at RFPP"; it was not.
If you needed to revert, the last stable revision was this one. — kashmīrī ^TALK 12:52, 3 December 2023 (UTC)[reply]

Considering that DQ blocked the IP range and fully protected the article, that certainly qualifies as overkill if ever there was. 2A00:23C8:9883:2601:2DCD:38D:854B:47E2 (talk) 13:30, 3 December 2023 (UTC)[reply]

The IP editor was blocked 45 minutes after USB4 was protected for their behavior subsequent to the page protection. Daniel Quinlan (talk) 23:35, 3 December 2023 (UTC)[reply]

I've lifted the full protection as it is hopefully unnecessary now, but the

bitey and concerning. Specifically, telling a new editor in an edit summary to RTFSP and LEAD SECTION IS FOR LAY PEOPLE AND MUST USE LAY LANGUAGE is not exactly conducive to making forward progress on an article, even if there are problems with the new editor's additions and behavior. If you find yourself nearing the point where you're ready to start shouting in edit summaries, it's an opportunity to use the talk page and have a discussion. Daniel Quinlan (talk) 23:28, 3 December 2023 (UTC)[reply

]

Daniel Quinlan, I get you, but how do you know that an IP editor is a new editor? How do you know their editing time on Wikipedia? Also, this was the second time I had to include this comment in edit summary, because they seemingly ignored the previous summary. Yes, the problem with the editor was that they ignore much of Wikipedia policies, guidelines and style guides, and instead use Wikipedia to publish poorly executed original research – their own interpretation of selected primary sources.
I have now restored the last stable version before the article got massacred by the IP editor. Feel free to institute temporary semi protection as requested. Cheers, — kashmīrī ^TALK 00:53, 4 December 2023 (UTC)[reply]

I don't know with certainty whether they're a new editor, but that is my impression. When you have some time, please read through the

WP:BITEY

article. The issues you're citing are good reasons to open discussions on the article talk page or a user talk page, not reasons to escalate in edit summaries.

You might consider reviewing the changes to see what might be improved and integrated into the article as an alternative to restoring such an old version of the article. Daniel Quinlan (talk) 01:11, 4 December 2023 (UTC)[reply]

Daniel Quinlan, That was three-week-old version of an article that was hardly getting one edit per week on average prior to the recent problematic spree by the IP editor. That stable version was certainly much better than what the IP editor has turned the article into.
Yes, some edits could potentially be incorporated in the article, but as you can see in the sections above, the editor focuses on interpretations of primary sources with a solitary aim to disprove any claims that USB4 could be in any way based on Thunderbolt. It's unclear why they are so bent on it, whether they have any vested interest or not (sure, I'm vaguely aware of the whole intellectual property aspects, royalties, patents, etc.). However, to-date nearly all of their editing was attempts to convince the reader that USB4 is not based on Thunderbolt specifications, even as other editors offered sources for such claims.
Personally, I don't care about it. However, IMO the reader should not be stuffed with such painfully detailed original research into the wording of original specifications, or speed calculations as a "proof" of something they would most likely not care about, either. Especially in the lead section.
The editor has no User Talk page, regretfully, although it would be ideal to discuss WP editing policies with them on Talk. — kashmīrī ^TALK 12:28, 4 December 2023 (UTC)[reply]