Alpha 21464

The Alpha 21464 is an unfinished

The 21464's origins began in the mid-1990s when computer scientist Joel Emer was inspired by Dean Tullsen's research into simultaneous multithreading (SMT) at the University of Washington. Emer had researched the technology in the late 1990s and began to promote it once he was convinced of its value. Compaq made the announcement that the next Alpha microprocessor would use SMT in October 1999 at Microprocessor Forum 1999.^[3] At that time, it was expected that systems using the Alpha 21464 would ship in 2003.^[3]

The microprocessor was an eight-issue

Implementing SMT required the replication of certain resources such as the

The integer execution unit made use of a new structure: the register cache. The register cache was not meant to mitigate the three tick register file latency (as some reports have claimed), but to reduce the complexity of operand bypass management. The register cache held all the results produced by the ALU and Load pipes for the previous N cycles. (N was something like 8.) The register cache structure was an architectural relabeling of what previous processors had implemented as a distributed mux.

The system interface was similar to that of the Alpha 21364. There were integrated memory controllers that provided ten RDRAM channels. Multiprocessing was facilitated by a router that provided links to other 21464s, and it architecturally supported 512-way multiprocessing without glue logic.

It was to be implemented in a 0.125 μm (sometimes referred to as 0.13 μm)

Tarantula was the code-name for an extension of the Alpha architecture under consideration and a derivative of the Alpha 21464 that implemented the aforementioned extension. It was canceled while still in development, before any implementation work had started, and before the 21464 was finished. The extension was to provide Alpha with a vector processing capability. It specified thirty-two 64 by 128-bit (8,192-bit or 1 KB) vector registers, approximately 50 vector instructions, and an unspecified number of instructions for moving data to and from the vector registers. Other EV8 follow-up candidates included a multicore design with two EV8 cores and a 4.0 GHz operating frequency.^{[citation needed]}

• "Alpha 21464 Targets 1.7 GHz in 2003".
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