Kendall Square Research

KSR1 logo

Kendall Square Research (KSR) was a supercomputer company headquartered originally in Kendall Square in Cambridge, Massachusetts in 1986, near Massachusetts Institute of Technology (MIT). It was co-founded by Steven Frank^[1] and Henry Burkhardt III, who had formerly helped found Data General and Encore Computer and was one of the original team that designed the PDP-8. KSR produced two models of supercomputer, the KSR1 and KSR2. It went bankrupt in 1994.

Technology

The KSR systems ran a specially customized version of the

million instructions per second (MIPS) and 40 million floating-point operations per second (MFLOPS). Up to 1088 of these processors could be arranged in a single system, with a minimum of eight. The KSR2 doubled the clock rate to 40 MHz and supported over 5000 processors. The KSR-1 chipset was fabricated by Sharp Corporation while the KSR-2 chipset was built by Hewlett-Packard

.

Software

Besides the traditional

multithreading

manager.

Hardware

The KSR-1 processor was implemented as a four-chip set in 1.2 micrometer complementary metal–oxide–semiconductor (

floating point unit is discussed below. The XIO had the capacity of 30 MB

/s throughput to I/O devices. It included 64 control and data registers.

The KSR processor was a 2-wide VLIW, with instructions of 6 types: memory reference (load and store), execute, control flow, memory control, I/O, and inserted. Execute instructions included arithmetic, logical, and type conversion. They were usually triadic

instructions were two cycles. The programmer (or compiler) could implicitly control the quashing behavior of the subsequent two instructions that would be initiated during the branch. The choices were: always retain the results, retain results if branch test is true, or retain results if branch test is false. Memory control provided synchronization primitives. I/O instructions were provided. Inserted instructions were forced into a flow by a coprocessor. Inserted load and store were used for direct memory access (DMA) transfers. Inserted memory instructions were used to maintain cache coherency. New coprocessors could be interfaced with the inserted instruction mechanism. IEEE standard floating point

arithmetic was supported. Sixty-four 64-bit wide registers were included.

The following example of KSR assembly performs an indirect procedure call to an address held in the procedure's constant block, saving the return address in register c14. It also saves the frame pointer, loads integer register zero with the value 3, and increments integer register 31 without changing the condition codes. Most instructions have a

interlocked, so must be scheduled explicitly, else the resulting hazard

means wrong values are sometimes loaded.

finop			; movb8_8 %i2,%c10
finop			; cxnop
finop			; cxnop
add8.ntr 75,%i31,%i31	; ld8 8(%c10),%c4
finop			; st8 %fp,504(%sp)
finop                   ; cxnop
movi8 3, %i0            ; jsr %c14,16(%c4)

In the KSR design, all of the memory was treated as cache. The design called for no home location- to reduce storage overheads and to software transparently, dynamically migrate/replicate memory based on where it was utilized; a Harvard architecture, separate bus for instructions and memory was used. Each node board contained 256 KB of I-cache and D-cache, essentially primary cache. At each node was 32 MB of memory for main cache. The system level architecture was shared virtual memory, which was physically distributed in the machine. The programmer or application only saw one contiguous address space, which was spanned by a 40-bit address. Traffic between nodes traveled at up to 4 gigabytes per second. The 32 megabytes per node, in aggregate, formed the physical memory of the machine.

Specialized

FDDI, and HIPPI

were supported.

History

As the company scaled up quickly to enter production, they moved in the late 1980s to 170 Tracer Lane, Waltham, Massachusetts.

KSR refocused its efforts from the scientific to the commercial marketplace, with emphasis on parallel relational databases and OLTP operations. It then got out of the hardware business, but continued to market some of its data warehousing and analysis software products.

The first KSR1 system was installed in 1991. With new processor hardware, new memory hardware and a novel memory architecture, a new compiler port, a new port of a relatively new operating system, and exposed memory hazards, early systems were noted for frequent system crashes. KSR called their cache-only memory architecture (COMA) by the trade name Allcache; reliability problems with early systems earned it the nickname Allcrash, although memory was not necessarily the root cause of crashes. A few KSR1 models were sold, and as the KSR2 was being rolled out, the company collapsed amid accounting irregularities involving the overstatement of revenue.

KSR used a proprietary processor because 64-bit processors were not commercially available. However, this put the small company in the difficult position of doing both processor design and system design. The KSR processors were introduced in 1991 at 20 MHz and 40 MFlops. At that time, the 32-bit

Intel 80486 ran at 50 MHz and 50 MFlops. When the 64-bit DEC Alpha

was introduced in 1992, it ran at up to 192 MHz and 192 MFlops, while the 1992 KSR2 ran at 40 MHz and 80 MFlops.

One customer of the KSR2, the Pacific Northwest National Laboratory, a United States Department of Energy facility, purchased an enormous number of spare parts, and kept their machines running for years after the demise of KSR.

KSR, along with many of its competitors (see below), went bankrupt during the collapse of the supercomputer market in the early 1990s. KSR went out of business in February 1994, when their stock was delisted from the stock exchange.

Competition

KSR's competitors included MasPar Computer Corporation, Thinking Machines, Meiko Scientific, and various old-line (and still surviving) companies like IBM and Intel.

References

^ "Virtual Shared Memory Symposium". Retrieved 2009-01-23.