POWER4
RS64 | |
| Successor(s) | POWER5 |
|---|---|
| POWER, PowerPC, and Power ISA architectures |
|---|
| NXP (formerly Freescale and Motorola) |
| IBM |
|
| IBM/Nintendo |
| Other |
| Related links |
| Cancelled in gray, historic in italic |
The POWER4 is a
Functional layout
The POWER4 has a unified L2 cache, divided into three equal parts. Each has its own independent L2 controller which can feed 32 bytes of data per cycle.[clarification needed] The Core Interface Unit (CIU) connects each L2 controller to either the data cache or instruction cache in either of the two processors. The Non-Cacheable (NC) Unit is responsible for handling instruction serializing functions and performing any noncacheable operations in the storage topology. There is an L3 cache controller, but the actual memory is off-chip. The GX bus controller controls I/O device communications, and there are two 4-byte wide GX buses, one incoming and the other outgoing. The Fabric Controller is the master controller for the network of buses, controlling communications for both L1/L2 controllers, communications between POWER4 chips {4-way, 8-way, 16-way, 32-way} and POWER4 MCM's. Trace-and-Debug, used for First Failure Data Capture, is provided. There is also a Built In Self Test function (BIST) and Performance Monitoring Unit (PMU). Power-on reset (POR) is supported.
Execution units
The POWER4 implements a
using eight independent execution units. They are: two floating-point units (FP1-2), two load-store units (LD1-2), two fixed-point units (FX1-2), a branch unit (BR), and a conditional-register unit (CR). These execution units can complete up to eight operations per clock (not including the BR and CR units):- each floating point unit can complete one fused multiply–addper clock (two operations),
- each load–store unit can complete one instruction per clock,
- each fixed-point unit can complete one instruction per clock.
The pipeline stages are:
- Branch Prediction
- Instruction Fetch
- Decode, Crack and Group Formation
- Group Dispatch and Instruction Issue
- Load–Store Unit Operation
- Load Hit Store
- Store Hit Load
- Load Hit Load
- Instruction Execution Pipeline
Multi-chip configuration
The POWER4 also came in a configuration using a multi-chip module (MCM) containing four POWER4 dies in a single package, with up to 128 MB of shared L3 ECC cache per MCM.
Parametrics
| Clock GHz | 1.3 GHz | |
|---|---|---|
| Power | 115 W | 1.5 V @ 1.1 GHz |
| Transistors | 174 million | |
| Gate L | 90 nm | |
| Gate oxide | 2.3 nm | |
| Metal-layer | pitch | thickness |
| M1 | 500 nm | 310 nm |
| M2 | 630 nm | 310 nm |
| M3-M5 | 630 nm | 20 nm |
| M6(MQ) | 1260 nm | 920 nm |
| M7(LM) | 1260 nm | 920 nm |
| Dielectric | ~4.2 | |
| Vdd | 1.6 V |
POWER4+
The POWER4+, released in 2003, was an improved version of the POWER4 that ran at up to 1.9 GHz.[3] It contained 184 million transistors, measured 267 mm2, and was fabricated in a 0.13 µm SOI CMOS process with eight layers of copper interconnect.
See also
Notes
- ^ "IBM's Server Processors: The RS64 and the POWER". The CPU Shack Museum. 2011-01-24. Retrieved 2015-04-17.
- ^ William Stallings, Computer Organization and Architecture, Seventh Edition, -pp 44
- ^ "IBM POWER Roadmap" (PDF). Speleotrove. IBM. 2006. p. 2. Retrieved 6 March 2018.
References
- "Power4 Focuses on Memory Bandwidth". (6 October 1999). Microprocessor Report.
- "IBM's Power4 Unveiling Continues". (20 November 2000). Microprocessor Report.
- "POWER4 System Microarchitecture" (PDF). IBM. Archived from the original (PDF) on 2013-11-07. Retrieved 2012-06-07.
- J. M. Tendler; J. S. Dodson; J. S. Fields, Jr.; H. Le & B. Sinharoy (2002). "POWER4 system microarchitecture". IBM Journal of Research and Development. 46 (1): 5–26. ISSN 0018-8646. Retrieved 2006-07-21.
- J. D. Warnock; J. M. Keaty; J. Petrovick; J. G. Clabes; C. J. Kircher; B. L. Krauter; P. J. Restle; B. A. Zoric & C. J. Anderson (2002). "The circuit and physical design of the POWER4 microprocessor". IBM Journal of Research and Development. 46 (1): 27–52. ISSN 0018-8646. Retrieved 2006-07-21.