PowerPC 600
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The PowerPC 600 family was the first family of PowerPC processors built. They were designed at the Somerset facility in Austin, Texas, jointly funded and staffed by engineers from IBM and Motorola as a part of the AIM alliance. Somerset was opened in 1992 and its goal was to make the first PowerPC processor and then keep designing general purpose PowerPC processors for personal computers. The first incarnation became the PowerPC 601 in 1993, and the second generation soon followed with the PowerPC 603, PowerPC 604 and the 64-bit PowerPC 620.
POWER, PowerPC, and Power ISA architectures |
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NXP (formerly Freescale and Motorola) |
IBM |
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IBM/Nintendo |
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Cancelled in gray, historic in italic |
Nuclear family
CPU | Pipeline stages | Misc |
---|---|---|
PowerPC 601 | 4 | 3 execution units, static branch prediction. SMP support. |
PowerPC 603 | 4 | 5 execution units, branch prediction. No SMP. |
PowerPC 604 | 6 | Superscalar, out-of-order execution, 6 execution units. SMP support. |
PowerPC 620 | 5 | Out-of-order execution- SMP support. |
PowerPC 601
The PowerPC 601 was the first generation of microprocessors to support the basic
60x bus
In order to help the effort to rapidly incorporate the
Using the 88110 bus as the basis for the 60x bus helped schedules in a number of ways. It helped the Apple Power Macintosh team by reducing the amount of redesign of their support ASICs and it reduced the amount of time required for the processor designers and architects to propose, document, negotiate, and close a new bus interface (successfully avoiding the "Bus Wars" expected by the 601 management team if the 88110 bus or the previous RSC buses hadn't been adopted). Worthy to note is that accepting the 88110 bus for the benefit of Apple's efforts and the alliance was at the expense of the first IBM RS/6000 system design team's efforts who had their support ASICs already implemented around the RSC's totally different bus structure.
This 60x bus later became a fairly long lived basic interface for the many variants of the 601, 603, 604, G3, G4 and Motorola/Freescale PowerQUICC processors.
Design
The chip was designed to suit a wide variety of applications and had support for external
First launched in IBM systems in the fall of 1993, it was marketed by IBM as the PPC601 and by Motorola as the MPC601. It operated at speeds ranging from 50 to 80 MHz. It was fabricated using a 0.6 μm
IBM was the sole manufacturer of the 601 and 601+ microprocessors in its Burlington, Vermont and East Fishkill, New York production facilities. The 601 used the IBM CMOS-4s process and the 601+ used the IBM CMOS-5x process. An extremely small number of these 601 and 601+ processors were relabeled with Motorola logos and part numbers and distributed through Motorola. These facts are somewhat obscured given there are various pictures of the "Motorola MPC601", particularly one specific case of masterful Motorola marketing where the 601 was named one of Time Magazine's 1994 "Products of the Year" with a Motorola marking.
PowerPC 601v
An updated version, the PowerPC 601v or PowerPC 601+, operating at 90 to 120 MHz was introduced in 1994. It was fabricated in a newer 0.5 μm CMOS process with four levels of interconnect, resulting in a die measuring 74 mm2. The 601+ design was remapped from CMOS-4s to CMOS-5x by an IBM-only team. To avoid time-to-market delays from design tool changes and commonizing fab groundrules, both the 601 and 601+ were designed with IBM EDA tools on IBM systems and were fabricated in IBM-only facilities.[3][4][5][6]
PowerPC 603
The PowerPC 603 was the first processor implementing the complete 32-bit PowerPC Architecture as specified. Introduced in 1994, it was an advanced design for its day, being one of the first microprocessors to offer dual issue (up to three with branch folding) and out-of-order execution combined with low power consumption of 2.2 W and a small die of 85 mm2.[7][8][9][10] It was designed to be a low cost, low power processor for portable applications. One of the main features was power saving functions (doze, nap and sleep mode) that could dramatically reduce power requirements, drawing only 2 mW in sleep mode. The 603 has a four-stage pipeline and five execution units: integer unit, floating-point unit, branch prediction unit, load/store unit and a system registry unit. It has separate 8 KB L1 caches for instructions and data and a 32/64 bit 60x memory bus, reaching up to 120 MHz at 3.8 V.[10] The 603 core did not have hardware support for SMP.
The PowerPC 603 had 1.6 million transistors and was fabricated by IBM and Motorola in a 0.5 μm CMOS process with four levels of interconnect. The die was 85 mm2 large drawing 2.2 W at 80 MHz.[10][11] The 603 architecture is the direct ancestor to the PowerPC 750 architecture, marketed by Apple as the PowerPC "G3".
The 603 was intended to be used for portable
PowerPC 603e and 603ev
The performance issues of the 603 were addressed in the PowerPC 603e. The L1 cache was enlarged and enhanced to 16 KB four-way set-associative data and instruction caches. The clock speed of the processors was doubled too, reaching 200 MHz. Shrinking the fabrication process to 350 nm allowed for speeds of up to 300 MHz. This part is sometimes called PowerPC 603ev. The 603e and 603ev have 2.6 million transistors each and are 98 mm2 and 78 mm2 large respectively. The 603ev draws a maximum of 6 W at 300 MHz.[18][19]
The PowerPC 603e was the first mainstream desktop processor to reach 300 MHz, as used in the
G2
The PowerPC 603e core, renamed G2 by
e300
Freescale has enhanced the 603e core, calling it e300, in the
PowerPC 604
The PowerPC 604 was introduced in December 1994 alongside the 603 and was designed as a high-performance chip for
The 604 is a
The PowerPC 604 contains 3.6 million transistors and was fabricated by IBM and Motorola with a 0.5 μm CMOS process with four levels of interconnect. The die measured 12.4 mm by 15.8 mm (196 mm2) and drew 14-17 W at 133 MHz. It operated at speeds between 100 and 180 MHz.[22][23][24]
PowerPC 604e
The PowerPC 604e was introduced in July 1996 and added a condition register unit and separate 32 KB data and instruction L1 caches among other changes to its memory subsystem and branch prediction unit, resulting in a 25% performance increase compared to its predecessor. It had 5.1 million transistors and was manufactured by IBM and Motorola on a 0.35 μm CMOS process with five levels of interconnect. The die was 148 mm2 or 96 mm2 large, manufactured by Motorola and IBM respectively, drawing 16–18 W at 233 MHz. It operated at speeds between 166 and 233 MHz and supported a memory bus up to 66 MHz.[25][26]
PowerPC 604ev "Mach5"
The PowerPC 604ev, 604r or "Mach 5" was introduced in August 1997 and was essentially a 604e fabricated by IBM and Motorola with a newer process, reaching higher speeds with a lower energy consumption. The die was 47 mm2 small manufactured on a 0.25 μm CMOS process with five levels of interconnect, and drew 6 W at 250 MHz. It operated at speeds between 250 and 400 MHz and supported a memory bus up to 100 MHz.
While Apple dropped the 604ev in 1998 in favor for the
PowerPC 620
The PowerPC 620 was the first implementation of the entire
The 620 was produced by Motorola in a 0.5 μm process. It had 6.9 million transistors and the die had an area of 311 mm2. It operated at clock rates between 120 and 150 MHz, and drew 30 W at 133 MHz. A later model was built using a 0.35 μm process, enabling it to reach 200 MHz.[further explanation needed]
The 620 was similar to the 604. It has a five-stage pipeline, same support for symmetric multiprocessing and the same number of execution units; a load/store unit, a branch unit, an FPU, and three integer units. With larger 32 KB instruction and data caches, support for a L2 cache that may have a capacity of 128 MB, and more powerful branch and load/store units that had more buffers, the 620 was very powerful. The branch history table was also larger and could dispatch more instructions so that the processor can handle out-of-order execution more efficiently than the 604. The floating-point unit was also enhanced compared to the 604. With a faster fetch cycle and support for several key instructions in hardware (like sqrt) made it, combined with faster and wider data buses, more efficient than the FPU in the 604.[further explanation needed]
6XX and GX buses
The system bus was a wider and faster 128-bit memory bus called the 6XX bus. It was designed to be a system bus for multiprocessor systems where processors, caches, memory and I/O was to be connected, assisted by a system control chip. It supports both 32- and 64-bit PowerPC processors, memory addresses larger than 32 bits, and
- Contribution to the history of Unix at Bull (Interesting reading concerning the use of PowerPC 620 at Bull. In French)
Extended family
PowerPC 602
The PowerPC 602 was a stripped-down version of PowerPC 603, specially made for game consoles by Motorola and IBM, introduced in February 1995.[29] It has smaller L1 caches (4 KB instruction and 4 KB data), a single-precision floating-point unit[29] and a scaled back branch prediction unit. It was offered at speeds ranging from 50 to 80 MHz, and drew 1.2 W at 66 MHz. It consisted of 1 million transistors and it was 50 mm2 large manufactured in a 0.5 μm, CMOS process with four levels of interconnect.[30]
3DO developed the M2 game console that used two PowerPC 602,[29][31] but it was never marketed.
PowerPC 603q
On October 21, 1996, the
The 603q was designed for Motorola, but they withdrew from the contract before the 603q went into full production. As a result, the 603q was canceled as QED could not continue to market the processor since they lacked a PowerPC license of their own.
PowerPC 613
"PowerPC 613" seems to be a name Motorola had given a third generation PowerPC.
PowerPC 614
Similar to PowerPC 613, the "PowerPC 614" might have been a name given by Motorola to a third generation PowerPC,[34][36] and later renamed by the same reason as 613. It's been suggested that the part was renamed "PowerPC 7400", and Motorola even bumped it to the fourth generation PowerPC even though the architectural differences between "G3" and "G4" was small. There are hardly any sources confirming any of this though and it might be pure speculation, or a reference to a completely different processor.
PowerPC 615
The "PowerPC 615" is a PowerPC processor announced by IBM in 1994, but which never reached mass production. Its main feature was to incorporate an x86 core on die, thus making the processor able to natively process both PowerPC and x86 instructions.[37] An operating system running on PowerPC 615 could either choose to execute 32-bit or 64-bit PowerPC instructions, 32-bit x86 instructions or a mix of three. Mixing instructions would involve a context switch in the CPU with a small overhead. The only operating systems that supported the 615 were Minix and a special development version of OS/2.[38]
It was 330 mm2 large and manufactured by IBM on a 0.35 μm process. It was pin compatible with Intel's Pentium processors and comparable in speed. The processor was introduced only as a prototype and the program was killed in part by the fact that Microsoft never supported the processor. Engineers working on the PowerPC 615 would later find their way to Transmeta, where they worked on the Crusoe processor. With progress having been demonstrated in the development of dynamic translation software, such as Digital's FX!32 technology, skepticism was expressed about dedicating hardware resources to running foreign binaries when such resources could be used to improve native performance instead, this also benefiting the performance of translated binaries.[39]: 94
PowerPC 625
"PowerPC 625" was the early name for the Apache series 64-bit PowerPC processors, designed by IBM based on the "Amazon" PowerPC-AS instruction set. They were later renamed "
PowerPC 630
"PowerPC 630" was the early name for the high end 64-bit PowerPC processor, designed by IBM to unify the
PowerPC 641
"PowerPC 641", codename Habanero, is a defunct PowerPC project by IBM in the 1994–96 timeframe. It has been suggested that was the third generation PowerPC based on the 604 processor.[40][41]
See also
- PowerPC 970
- IBM POWER Instruction Set Architecture
- IBM Power microprocessors
- Power ISA
- List of Macintosh models grouped by CPU type
References
- ^ Stokes, Jon (August 3, 2004). "PowerPC on Apple: An Architectural History, Part I (page 2, "PowerPC 601")". Ars Technica.
- ^ "The Bus Interface for 32-Bit Microprocessors" (PDF). Motorola. 1997.
- ^ Allen, M.; Becker, M (February 1993). Multiprocessing Aspects of the PowerPC 601 Microprocessor. Compcon. pp. 117–126.
- S2CID 26895845.
- ^ Moore, C.R. (February 1993). The PowerPC 601 Microprocessor. Compcon. pp. 109–116.
- ^ "PowerPC 601 Microprocessor". Archived from the original on February 7, 2009.
- ^ Pham et al., "A 3.0 W 75 SPECint92 85 SPECfp92 Superscalar RISC Microprocessor", ISSC Digest Of Technical Papers, pp. 212–213, Feb. 1994.
- ^ Burgess et al., "The PowerPC 603 Microprocessor: A High Performance, Low Power, Superscalar RISC Microprocessor", Proceedings of COMPCON '94, Feb. 1994.
- ^ Gary et al., "The PowerPC 603 Microprocessor: A Low-Power Design For Portable Applications", Proceedings of COMPCON '94, Feb. 1994.
- ^ a b c Gerosa et al., "A 2.2 W, 80 MHz Superscalar RISC Microprocessor", IEEE Journal of Solid-State Circuits, vol. 29, pp. 1440–1454, Dec. 1994.
- ^ James Kahle; Deene Ogden. "PowerPC 603 Microprocessor". IBM. Archived from the original on August 6, 1997.
- S2CID 51808955. Archived from the original(PDF) on July 30, 2018.
The 603's tiny 8K caches were notoriously poor for Mac OS software, particularly for 68K emulation; even the 603e's caches cause a significant performance hit at higher clock speeds. Given Arthur's design target of 250 MHz and up, doubling the caches again made sense.
- ^ Jansen, Daniel (2014). "CPUs: PowerPC 603 and 603e". Low End Mac. Retrieved 29 July 2018.
- ^ Barber, Scott (1997). "Performa and Power Mac x200 Issues". Low End Mac. Retrieved 29 July 2018.
- ^ Davison, Remy. "The 10 Worst Macs Ever Built". Insanely Great Mac. Archived from the original on February 1, 2010. Retrieved July 30, 2018.
- ^ Knight, Daniel (2014). "Power Mac and Performa x200, Road Apples". Low End Mac. Retrieved 29 July 2018.
- ^ "Performa 5200". Low End Mac. 1995. Retrieved 29 July 2018.
- ^ "Freescale's 603e page". Freescale Semiconductor.
- ^ "IBM's 603e page". Archived from the original on February 7, 2009.
- ^ LeCroy 1998 Test & Measurement Products Catalog, TMCAT98 0498
- ^ LeCroy 2001 Test and Measurement Products Catalog
- ^ Stokes, Jon (August 3, 2004). "PowerPC on Apple: An Architectural History, Part I (page 6, The PowerPC 604)". Ars Technica.
- ^ Gwennap, Linley (April 18, 1994). "PPC 604 Powers Past Pentium". Microprocessor Report. 8 (5).
- S2CID 11603864.
- ^ "IBM's PowerPC 604e page". IBM.[dead link]
- ^ "NXP's PowerPC 604e page".
- ^ "IBM trashes PowerPC 620 system plans". Tech Monitor. New Statesman Media Group Ltd. August 25, 1997. Retrieved March 20, 2021.
- ^ Thompson, Tom; Ryan, Bob. "PowerPC 620 Soars". Byte. Archived from the original on December 20, 1996.
- ^ Imagine Media: 36–40. June 1995.
- ^ "PowerPC 602 RISC Microprocessor Hardware Specification" (PDF). Archived from the original (PDF) on 2016-08-07. Retrieved 2016-07-24.
- ^ 3DO/Matsushita M2 Console Information
- ^ "QED Announces PowerPC Microprocessor Technology Development In Addition To Existing MIPS Microprocessors" (Press release). Quantum Effect Devices. October 21, 1996. Archived from the original on July 12, 2007.
- ^ Turley, Jim (November 18, 1996). "QED's PowerPC 603q Heads for Low Cost". Microprocessor Report: 22–23.
- ^ a b PowerPC revving up for next generation – Speedier RISC ahead through '97
- ^ Art Arizpe -Project Manager/Engineering Manager Motorola, 1991–1996
- ^ a b Processor Codenames – PowerPC's
- ^ Halfhill, Tom R. "Alternate Views of the 615". Byte. Archived from the original on December 20, 1996.
- ^ "Microsoft killed the PowerPC 615". The Register. October 1, 1998.
- ^ "DEC Unveils FX!32 Tech". Electronic News. 6 November 1995. pp. 1, 94. Retrieved 12 October 2022.
- ^ "Charles Moore's resume" (PDF). Archived from the original (PDF) on July 24, 2011.
- ^ Every, David K. (1999). "G3's - they just keep getting better". Archived from the original on October 10, 1999.
Further reading
- Weiss, Shlomo; Smith, James Edward (1994). POWER and PowerPC. Morgan Kaufmann. ISBN 1558602798. — Relevant parts: Chapter 8 (describes the PowerPC 601), and Chapter 11 (a comparison of the PowerPC 601 and Alpha 21064)