Titan (processor)
| POWER, PowerPC, and Power ISA architectures |
|---|
| NXP (formerly Freescale and Motorola) |
| IBM |
|
| IBM/Nintendo |
| Other |
| Related links |
| Cancelled in gray, historic in italic |
Titan was a planned family of
32-bit Power ISA-based microprocessor cores designed by Applied Micro Circuits Corporation (AMCC), but was scrapped in 2010.[1] Applied Micro chose to continue development of the PowerPC 400
core instead, on a 40 nm fabrication process.
Details
It was designed to be the foundation of
dual core
SoC implementations consuming less than 15 W. There were plans for single, dual and quad-core versions.
The Titan had a new superscalar, out of order 8-9 stage core with a novel three-stage CPU cache design. Small 4/4 KiB instruction and data caches at "level 0" sit before the traditional 32/32 KiB L1 caches up to 1 MB L2 cache that will be shared between all cores (supporting up to four). The Titan was compliant with the Power ISA v.2.04.
Implementations
- APM 83290 – The first implementations of the Titan core design, codenamed Gemeni.[2] Two 1.5 GHz cores with FPU, 512 kB shared L2 cache, DDR2 controller, security engine, multi-channel DMA and I/O engine for gigabit Ethernet, PCIe, USB, RapidIO and SATA. It began sampling in October 2009 [1]. The processor is aimed at telecom and control plane applications. It is built using TSMC's 90 nm bulk CMOS fabrication to reduce cost.[2] Archived 2011-08-18 at the Wayback Machine
References
- ^ "AMCC takes another shot at multicore". EETimes. 2010-09-27. Retrieved 2011-07-14.
- ^ "AMCC, TSMC put new MPU spin on IBM technology". EETimes. 2009-09-25. Retrieved 2011-07-14.