PowerPC 970
90 nm | |
Microarchitecture | ppc970, POWER4 |
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Instruction set | 32/64-bit PowerPC 2.01 |
Physical specifications | |
Cores |
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Products, models, variants | |
Variant(s) |
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History | |
Predecessor(s) | POWER4 |
POWER, PowerPC, and Power ISA architectures |
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NXP (formerly Freescale and Motorola) |
IBM |
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IBM/Nintendo |
Other |
Related links |
Cancelled in gray, historic in italic |
The PowerPC 970, PowerPC 970FX, and PowerPC 970MP are
Having created the PowerPC architecture in the early 1990s via the
IBM's JS20/JS21
Design
The PowerPC 970 is a single core derivative of the
Like the POWER4, the front-end is nine stages long. The PowerPC 970 can fetch and decode up to eight instructions, dispatch up to five to reserve stations, issue up to eight to the execution units and retire up to five per cycle. The execution pipelines were lengthened compared to the POWER4 to achieve higher IPC. It has eight execution units: two arithmetic logic units (ALUs), two double-precision floating-point units, two load/store units and two AltiVec units.[3]
One of the AltiVec units executes integer and floating-point instructions, and the other only permute instructions. The latter has three subunits for simple integer, complex integer and floating-point instructions. These units have pipelines of varying lengths: 10 stages for simple integer and permute instructions, 13 stages for complex integer instructions and 16 stage for floating-point instructions.[3]
The processor has two unidirectional 32-bit double data rate (DDR) buses (one for reads, the other for writes) to the system controller chip (northbridge) running at one quarter of the processor core speed. The buses also carry addresses and control signals in addition to data so only a percentage of the peak bandwidth can be realized (6.4 GB/s at 450 MHz). As the buses are unidirectional, each direction can realize only half the aggregate bandwidth, or 3.2 GB/s.[3]
Generations
All generations of 970 processors were manufactured in IBM's East Fishkill plant in New York on a white ceramic substrate that was typical for IBM's high end processors of the era.
PowerPC 970
The PowerPC 970 was announced by IBM in October 2002. It was released in Apple Computer's Power Mac G5 in June 2003. Like its naming convention of G3 and G4, Apple branded the PowerPC 970 based products as G5, for the fifth generation of PowerPC. IBM released its first PowerPC 970 blade servers, the BladeCenter JS20, in November 2003.
The PowerPC 970 has 512 KB of full-speed
PowerPC 970FX
The PowerPC 970FX has a
It has 10 functional units – 2 Fixed-Point Units, 2 Load/Store Units, 2 Floating Point Units, 1 Branch Unit, 1 SIMD ALU unit, 1 SIMD Permute unit, and 1 Condition Register. It supports up to 215 instructions in-flight: 16 in the Instruction Fetch Unit, 67 in the Instruction Decode Unit, 100 in the Functional Units, and 32 in the Store Queue. It has 64 KBs of directly mapped Instruction Cache and 32 KBs of D-Cache.[6]
Apple released 970FX-powered machines throughout 2004: the
Market demand was intense for a faster laptop CPU than the G4, but Apple never delivered a G5 series CPU in
PowerPC 970MP
IBM announced the PowerPC 970MP,
The PowerPC 970MP replaced the PowerPC 970FX in Apple's high-end Power Mac G5 computers, while the iMac G5 and the legacy PCI-X Power Mac G5 continued to use the PowerPC 970FX processor. The PowerPC 970MP is used in IBM's JS21 blade modules, IBM Intellistation POWER 185 workstation and YDL PowerStation by Fixstars Solutions (Yellow Dog Linux (YDL) PowerStation).
Due to high power requirements, IBM discontinued units above 2.0 GHz.
Northbridges
Two dedicated northbridges for PowerPC 970-based computers were manufactured by IBM:
- CPC925 – Designed by AppleECC memory). It is capable of supporting up to two PowerPC 970s or PowerPC 970FXs and has two 550 MHz unidirectional processor buses, a 400 MHz DDR memory controller, x8 AGP and a 400 MHz 16-bit HyperTransporttunnel. It fabricated on a 130 nm process. Additionally, there was an unreleased U3Lite northbridge in development for the PowerBook G5, which never made it to market.
- CPC945 – Designed by IBM and called U4 by Apple, it is capable of supporting two PowerPC 970MPs and has two 625 MHz unidirectional processor buses, two memory controllers that support up to 64 GB of 533 MHz DDR2 SDRAM with ECC capability and has a x16 PCIelane and an 800 MHz 16-bit HyperTransport tunnel. It is fabricated on a 90 nm process.
A CPC965 northbridge was canceled. Slated for release in 2007, it was to be a uniprocessor-only northbridge. Its features were a 533 MHz DDR2 controller that supported up to 8 GB ECC memory, a 8x PCIe bus, integrated four-port
Buses
IBM uses its proprietary Elastic Interface (EI) bus in the modules.
See also
- Supercomputers using the PowerPC 970:
- System X
- Some previous models of supercomputers in the Marenostrumversion 2.
- List of Macintosh models grouped by CPU type
References
- ^ "Apple Unleashes the World's Fastest Personal Computer—the Power Mac G5". Apple. June 23, 2003. Archived from the original on December 16, 2021. Retrieved December 4, 2017.
- ^ "Apple and IBM Introduce the PowerPC G5 Processor". Apple. June 23, 2003. Archived from the original on April 21, 2022. Retrieved December 4, 2017.
- ^ a b c Halfhill, Tom R. (October 28, 2002). "IBM Trims Power4, Adds AltiVec". Microprocessor Report.
- ^ a b c "IBM production dates CPU-World". Archived from the original on April 20, 2018. Retrieved March 2, 2013.
- ^ "IBM PowerPC 970FX RISC Microprocessor Datasheet" (PDF). 01.ibm.com. Retrieved November 2, 2010.
- ^ "IBM PowerPC 970FX RISC Microprocessor User's Manual V 1.7" (PDF). www-01.ibm.com. Archived (PDF) from the original on May 22, 2014. Retrieved May 21, 2014.
- ^ Paul Hales: Friday, July 8, 2005, 5:28 PM (July 8, 2005). "IBM introduces dual-core PowerPC 970 chip – The INQUIRER". Theinquirer.net. Archived from the original on August 12, 2006. Retrieved September 22, 2008.
{{cite web}}
: CS1 maint: multiple names: authors list (link) CS1 maint: numeric names: authors list (link) CS1 maint: unfit URL (link) - ^ "Next IBM-Apple chip getting high-end feature | Tech News on ZDNet". News.zdnet.com. Archived from the original on April 17, 2008. Retrieved September 22, 2008.
- ^ "IBM BladeCenter JS21 Express". 03.ibm.com. Archived from the original on September 10, 2007. Retrieved September 22, 2008.
- ^ Steve Jobs, Apple (June 25, 2003). "WWDC 2003 Keynote". Archived from the original on December 21, 2021. Retrieved October 16, 2009 – via YouTube.
- ^ LaPedus, Mark (March 10, 2006). "IBM rolls low-power processors, IP cores" Archived September 26, 2007, at the Wayback Machine. EE Times.
Further reading
- "IBM's PPC970 Becomes Apple's G5". (July 7, 2003). Microprocessor Report.
- "IBM Takes the Lead". (February 9, 2004). Microprocessor Report.
- "IBM's Double-Shot of PowerPC". (November 7, 2005). Microprocessor Report.