SuperH

SuperH (or SH) is a

The SuperH processor core family was first developed by

In the past, this sort of design problem would have been solved using microcode, with the low-end models in the series performing non-implemented instructions as a series of more basic instructions. For instance, a "long multiply" (multiplying two 32-bit registers to produce a 64-bit product) might be implemented in hardware on high-end models but instead be performed as a series of additions on low-end models.

One of the key realizations during the development of the

Delayed branches are introduced for both SH-1 and SH-2. Unconditional branch instructions have one delay slot.^[6]

A few years later, the SH-3 core was added to the family; new features included another interrupt concept, a memory management unit (MMU), and a modified cache concept. These features required an extended instruction set, adding six new instructions for a total of 68.^[3] The SH-3 was bi-endian, running in either big-endian or little-endian byte ordering.

The SH-3 core also added a

Between 1994 and 1996, 35.1 million SuperH devices were shipped worldwide.^[7]

In 1997, Hitachi and

In early 2001, Hitachi and STM formed the IP company SuperH, Inc., which was going to license the SH-4 core to other companies and was developing the SH-5 architecture, the first move of SuperH into the 64-bit area. The earlier SH-1 through 3 remained the property of Hitachi.^[8][9]

In 2003, Hitachi and

The SH-5 design supported two modes of operation: SHcompact mode, which is equivalent to the user-mode instructions of the SH-4 instruction set; and SHmedia mode, which is very different in that it uses 32-bit instructions with sixty-four 64-bit integer registers and

The last evolutionary step happened around 2003 where the cores from SH-2 up to SH-4 were getting unified into a superscalar SH-X core which formed a kind of instruction set superset of the previous architectures, and added support for symmetric multiprocessing.

Since 2010, the SuperH CPU cores, architecture and products are with

The last of the SH-2 patents expired in 2014. At

Several features of SuperH have been cited as motivations for designing new cores based on this architecture:[11]

• High
  ARM or MIPS^[15]
  important for cache and memory bandwidth performance
• Existing
  Windows Embedded, QNX^[13]
  )
• Extremely low ASIC
  fabrication
  costs now that the patents are expiring (around US$0.03 for a dual-core J2 core on TSMC's 180 nm process).
• Patent- and royalty-free (BSD-licensed) implementation
• Full and vibrant community support
• Availability of low cost hardware development platform for zero cost FPGA tools
• CPU and SoC RTL generation and integration tools, producing FPGA and ASIC portable RTL and documentation
• Clean, modern design with open source design, generation, simulation and verification environment

Models

Generation comparison^[16]

	Clock [MHz]	Computer performance			Image
		MIPS	MOPS	GFLOPS
SH-1	20	20
SH-2	28,7	78	120
SH-3	200	260	400
SH-4	200	480		1,9
SH-5	400	700	9600	2,8
SH-6		>2000	>24000	>7,0

The family of SuperH CPU cores includes:

• SH-1 – used in microcontrollers for deeply embedded applications (CD-ROM drives, major appliances, etc.)
• SH-2 – used in microcontrollers with higher performance requirements, networking applications, and also in video game consoles, like the
  Sega 32X add-on. The SH-2 has also found home in many automotive engine control unit applications, including Subaru, Mitsubishi, and Mazda
  .
• SH-2A – The SH-2A core is an extension of the SH-2 core including a few extra instructions but most importantly moving to a superscalar architecture (it is capable of executing more than one instruction in a single cycle) and two five-stage pipelines. It also incorporates 15 register banks to facilitate an interrupt latency of 6 clock cycles. It is also strong in motor control application but also in multimedia, car audio, powertrain, automotive body control and office + building automation
• SH-DSP – initially developed for the mobile phone market, used later in many consumer applications requiring DSP performance for JPEG compression etc.
• SH-3 – used for mobile and handheld applications such as the
  Sega NAOMI hardware's CPU, also made use of this CPU. The Korg Electribe EMX and ESX music production units also use the SH-3.^[17]
• SH-3-DSP – used mainly in multimedia terminals and networking applications, also in printers and fax machines
• SH-4 – used whenever high performance is required such as car multimedia terminals, video game consoles, most notably the Dreamcast, or set-top boxes
• SH-5 – used in high-end 64-bit multimedia applications
• SH-X – mainstream core used in various flavours (with/without DSP or FPU unit) in engine control unit, car multimedia equipment, set-top boxes or mobile phones
• SH-Mobile – SuperH Mobile Application Processor; designed to offload application processing from the baseband LSI

The SH-2 is a 32-bit RISC architecture with a 16-bit fixed instruction length for high code density and features a hardware

The SH-2 has a cache on all ROM-less devices.

It provides 16 general-purpose registers, a vector-base register, global-base register, and a procedure register.

Today the SH-2 family stretches from 32 KB of on-board flash up to ROM-less devices. It is used in a variety of different devices with differing peripherals such as CAN, Ethernet, motor-control timer unit, fast ADC and others.

The SH-2A is an upgrade to the SH-2 core that added some 32-bit instructions. It was announced in early 2006.

New features on the SH-2A core include:

• Superscalar architecture: execution of 2 instructions simultaneously
• Harvard architecture
• Two 5-stage pipelines
• Mixed 16-bit and 32-bit instructions
• 15 register banks for interrupt response in 6 cycles.
• Optional FPU

The SH-2A family today spans a wide memory field from 16 KB up to and includes many ROM-less variations. The devices feature standard peripherals such as

The SH-4 is a RISC CPU and was developed for primary use in multimedia applications, such as Sega's Dreamcast and NAOMI game systems. It includes a much more powerful floating-point unit^[note] and additional built-in functions, along with the standard 32-bit integer processing and 16-bit instruction size.

SH-4 features include:

• FPU with four floating-point multipliers, supporting 32-bit single-precision and 64-bit double-precision floats
• 4D floating-point
  matrix–vector multiplication
• 128-bit floating-point bus allowing 3.2 GB/sec transfer rate from the data cache
• 64-bit external data bus with 32-bit memory addressing, allowing a maximum of 4 GB addressable memory (see Byte addressing) with a transfer rate of 800 MB/sec
• Built-in interrupt, DMA, and power management controllers

^ There is no FPU in the custom SH-4 made for Casio, the SH7305.

The SH-5 is a 64-bit RISC CPU.^[18]

Almost no non-simulated SH-5 hardware was ever released,^[19] and, unlike the still-live SH-4, support for SH-5 was dropped from GCC^[20] and Linux.

SH-6 was an announced but never implemented further development. It was supposed to achieve over 2 GIPS, over 7 GFLOPS and over 24 GOPS.^[16]

• SuperH RISC Engine SH-1/SH-2 Programming Manual (PDF). Hitachi Americal Ltd. 3 September 1996. Retrieved 2020-12-06.
• SH-4 CPU Core Architecture (PDF). STMicroelectronics and Hitachi Ltd. 12 September 2002. ADCS 7182230F. Retrieved 2020-12-06.

• Renesas SuperH, Products, Tools, Manuals, App.Notes, Information
• J-core Open Processor
• J-core on GitHub
• Linux SuperH development list
• DCTP - Hitachi 200 MHz SH-4 at the Wayback Machine (archived August 10, 2016)
• in-progress Debian port for SH4
• Chen, Raymond (5 August 2019). "The SuperH-3, part 1: Introduction". The Old New Thing (blog). Retrieved 2024-01-22. A 15-part series on programming for the microprocessor.