Read-only memory

Strictly speaking, read-only memory refers to hard-wired memory, such as diode matrix or a mask ROM integrated circuit (IC), that cannot be electronically changed after manufacture. Although discrete circuits can be altered in principle, through the addition of bodge wires and the removal or replacement of components, ICs cannot. Correction of errors, or updates to the software, require new devices to be manufactured and to replace the installed device.

IBM used capacitor read-only storage (CROS) and transformer read-only storage (TROS) to store microcode for the smaller System/360 models, the 360/85, and the initial two System/370 models (370/155 and 370/165). On some models there was also a writeable control store (WCS) for additional diagnostics and emulation support. The Apollo Guidance Computer used core rope memory, programmed by threading wires through magnetic cores.

Solid-state ROM

The simplest type of

• It is only economical to buy mask ROM in large quantities, since users must contract with a
  foundry
  to produce a custom design for every piece, or revision of software.
• The turnaround time between completing the design for a mask ROM and receiving the finished product is long, for the same reason.
• Mask ROM is impractical for
  R&D
  work since designers frequently need to quickly modify the contents of memory as they refine a design.
• If a product is shipped with faulty mask ROM, the only way to fix it is to recall the product and physically replace the ROM in every unit shipped.

Subsequent developments have addressed these shortcomings.

Mask ROM is a read-only memory whose contents are programmed by the integrated circuit manufacturer (rather than by the user). The desired memory contents are furnished by the customer to the device manufacturer. The desired data is converted into a custom photomask/mask layer for the final metallization of interconnections on the memory chip (hence the name).

Mask ROM can be made in several ways, all of which aim to change the electrical response of a transistor when it is addressed on a grid, such as:

• In a ROM with transistors in a NOR configuration, using a photomask to define only specific areas of a grid with transistors, to fill with metal thus connecting to the grid only part of all the transistors in the ROM chip^[2] thus making a grid where transistors that are connected cause a different electrical response when addressed, than spaces in the grid where the transistors are not connected, a connected transistor may represent a 1 and an unconnected one a 0, or viceversa. This is the least expensive, and fastest way of making mask ROM^[2] as it only needs one mask with data, and has the lowest density of all mask ROM types as it is done at the metallization layer,^[2] whose features can be relatively large in respect to other parts of the ROM. This is known as contact-programmed ROM. In ROM with a NAND configuration, this is known as metal-layer programming and the mask defines where to fill the areas surrounding transistors with metal which short-circuits the transistors instead, a transistor that is not short circuited may represent a 0, and one that is may represent a 1, or viceversa.^[13]
• Using two masks to define two types of ion implantation regions for transistors, to change their electrical properties when addressed in a grid and define two types of transistors.^[2] The type of transistor defines if it represents a 1 or a 0 bit. One mask defines where to deposit one type of ion implantation (the "1" transistors), and another defines where to deposit the other (the "0" transistors). This is known as voltage threshold ROM (VTROM) as the different ion implantation types define different voltage thresholds in the transistors, and it's the voltage threshold on a transistor that defines a 0, or a 1. Can be used with NAND and NOR configurations. This technique offers a high level of resistance against optical reading of the contents as ion-implantation regions are difficult to distinguish optically,^[13] which may be attempted with decapping of the ROM and a microscope.
• Using two levels of thickness for a gate oxide in transistors,^[2] and using a mask to define where to deposit one thickness of oxide, and another mask to deposit the other. Depending on the thickness a transistor can have different electrical properties and thus represent either a 1 or a 0.
• Using several masks to define the presence or absence of the transistors themselves, on a grid. Addressing a non-existent transistor may be interpreted as a 0, and if a transistor is present it may be interpreted as a 1, or viceversa. This is known as active-layer programming.^[13]

Mask ROM transistors can be arranged in either NOR or NAND configurations and can achieve one of the smallest cell sizes possible as each bit is represented by only one transistor. NAND offers higher storage density than NOR. OR configurations are also possible, but compared to NOR it only connects transistors to V_cc instead of V_ss.

It is common practice to use rewritable non-volatile memory – such as UV-EPROM or EEPROM – for the development phase of a project, and to switch to mask ROM when the code has been finalized. For example, Atmel microcontrollers come in both EEPROM and mask ROM formats.

The main advantage of mask ROM is its cost. Per bit, mask ROM was more compact than any other kind of semiconductor memory. Since the cost of an integrated circuit strongly depends on its size, mask ROM is significantly cheaper than any other kind of semiconductor memory.

However, the one-time masking cost is high and there is a long turn-around time from design to product phase. Design errors are costly: if an error in the data or code is found, the mask ROM is useless and must be replaced in order to change the code or data.^[15]

As of 2003^[update], four companies produce most such mask ROM chips:

Some integrated circuits contain only mask ROM. Other integrated circuits contain mask ROM as well as a variety of other devices. In particular, many microprocessors have mask ROM to store their microcode. Some microcontrollers have mask ROM to store the bootloader or all of their firmware.

Classic mask-programmed ROM chips are integrated circuits that physically encode the data to be stored, and thus it is impossible to change their contents after fabrication.

It is also possible to write the contents of a Laser ROM by using a laser to alter the electrical properties of only some diodes on the ROM, or by using a laser to cut only some polysilicon links, instead of using a mask.^[17][18][13]

Field-programmable

• Programmable read-only memory (PROM), or one-time programmable ROM (OTP), can be written to or programmed via a special device called a PROM programmer. Typically, this device uses high voltages to permanently destroy or create internal links (fuses or antifuses
  ) within the chip. Consequently, a PROM can only be programmed once.
• Erasable programmable read-only memory (EPROM) can be erased by exposure to strong ultraviolet light (typically for 10 minutes or longer), then rewritten with a process that again needs higher than usual voltage applied. Repeated exposure to UV light will eventually wear out an EPROM, but the endurance of most EPROM chips exceeds 1000 cycles of erasing and reprogramming. EPROM chip packages can often be identified by the prominent quartz
  "window" which allows UV light to enter. After programming, the window is typically covered with a label to prevent accidental erasure. Some EPROM chips are factory-erased before they are packaged, and include no window; these are effectively PROM.
• Electrically erasable programmable read-only memory
  (EEPROM) is based on a similar semiconductor structure to EPROM, but allows its entire contents (or selected banks) to be electrically erased, then rewritten electrically, so that they need not be removed from the computer (whether general-purpose or an embedded computer in a camera, MP3 player, etc.). Writing or flashing an EEPROM is much slower (milliseconds per bit) than reading from a ROM or writing to a RAM (nanoseconds in both cases).
  • mains power and backed up with a lithium battery
    .
  • NOR flash
    memory is sometimes called flash ROM or flash EEPROM when used as a replacement for older ROM types, but not in applications that take advantage of its ability to be modified quickly and frequently.

By applying write protection, some types of reprogrammable ROMs may temporarily become read-only memory.

Other technologies

There are other types of non-volatile memory which are not based on solid-state IC technology, including:

• backwards-compatibility
  with CD-ROM.

• Diode matrix ROM, used in small amounts in many computers in the 1960s as well as electronic desk calculators and keyboard encoders for terminals. This ROM was programmed by installing discrete semiconductor diodes at selected locations between a matrix of word line traces and bit line traces on a printed circuit board.
• System/360 and complex peripheral devices stored their microcode in either capacitor (called BCROS for balanced capacitor read-only storage on the 360/50 and 360/65, or CCROS for card capacitor read-only storage on the 360/30) or transformer (called TROS for transformer read-only storage on the 360/20, 360/40
  and others) matrix ROM.
• MIT's Apollo Spacecraft Computers, DEC's PDP-8 computers, the Hewlett-Packard 9100A calculator, and other places. This type of ROM was programmed by hand by weaving "word line wires" inside or outside of ferrite transformer cores.^[20]
• Diamond Ring stores, in which wires are threaded through a sequence of large ferrite rings that function only as sensing devices. These were used in TXE telephone exchanges.

Speed

Although the relative speed of RAM vs. ROM has varied over time, as of 2007^[update] large RAM chips can be read faster than most ROMs. For this reason (and to allow uniform access), ROM content is sometimes copied to RAM or

shadowed

before its first use, and subsequently read from RAM.

Writing

For those types of ROM that can be electrically modified, writing speed has traditionally been much slower than reading speed, and it may need unusually high voltage, the movement of jumper plugs to apply write-enable signals, and special lock/unlock command codes. Modern NAND Flash can be used to achieve the highest write speeds of any rewritable ROM technology, with speeds as high as 10 GB/s in an SSD. This has been enabled by the increased investment in both consumer and enterprise solid state drives and flash memory products for higher end mobile devices. On a technical level the gains have been achieved by increasing parallelism both in controller design and of storage, the use of large DRAM read/write caches and the implementation of memory cells which can store more than one bit (DLC, TLC and MLC). The latter approach is more failure prone but this has been largely mitigated by overprovisioning (the inclusion of spare capacity in a product which is visible only to the drive controller) and by increasingly sophisticated read/write algorithms in drive firmware.

Endurance and data retention

Because they are written by forcing electrons through a layer of

disk drives in the near future.^{[citation needed}

]

The timespan over which a ROM remains accurately readable is not limited by write cycling. The data retention of EPROM, EAROM, EEPROM, and Flash may be time-limited by charge leaking from the

floating gates of the memory cell transistors. Early generation EEPROM's, in the mid-1980s generally cited 5 or 6 year data retention. A review of EEPROM's offered in the year 2020 shows manufacturers citing 100 year data retention. Adverse environments will reduce the retention time (leakage is accelerated by high temperatures or radiation). Masked ROM and fuse/antifuse PROM do not suffer from this effect, as their data retention depends on physical rather than electrical permanence of the integrated circuit, although fuse re-growth was once a problem in some systems.^[21]

Content images

Main article: ROM image

The contents of ROM chips can be extracted with special hardware devices and relevant controlling software. This practice is common for, as a main example, reading the contents of older video

game console cartridges

. Another example is making backups of firmware/OS ROMs from older computers or other devices - for archival purposes, as in many cases, the original chips are PROMs and thus at risk of exceeding their usable data lifetime.

The resultant memory dump files are known as ROM images or abbreviated ROMs, and can be used to produce duplicate ROMs - for example to produce new cartridges or as digital files for playing in console emulators. The term ROM image originated when most console games were distributed on cartridges containing ROM chips, but achieved such widespread usage that it is still applied to images of newer games distributed on CD-ROMs or other optical media.

ROM images of commercial games, firmware, etc. usually contain copyrighted software. The unauthorized copying and distribution of copyrighted software is a violation of copyright laws in many jurisdictions, although duplication for backup purposes may be considered fair use depending on location. In any case, there is a thriving community engaged in the distribution and trading of such software for preservation/sharing purposes.

Timeline

See also: Flash memory § Timeline, Random-access memory § Timeline, and Transistor count § Memory

Date of introduction	Chip name	Capacity (bits)	ROM type	MOSFET	Manufacturer(s)	Process	Area	Ref
1956	?	?	PROM	?	Arma	?	?	[3][4]
1965	?	256 bit	ROM	Bipolar TTL	Sylvania	?	?	[22]
1965	?	1 kb	ROM	MOS	General Microelectronics	?	?
1969	3301	1 kb	ROM	Bipolar	Intel	?	?	[22]
1970	?	512 bit	PROM	Bipolar TTL	Radiation	?	?	[7]
1971	1702	2 kb	EPROM	Static MOS ( silicon gate )	Intel	?	15 mm²	[7][23]
1974	?	4 kb	ROM	MOS	AMD, General Instrument	?	?	[22]
1974	?	?	EAROM	MNOS	General Instrument	?	?	[7]
1975	2708	8 kb	EPROM	NMOS (FGMOS)	Intel	?	?	[24][25]
1976	?	2 kb	EEPROM	MOS	Toshiba	?	?	[26]
1977	µCOM-43 (PMOS)	16 kb	PROM	PMOS	NEC	?	?	[27]
1977	2716	16 kb	EPROM	TTL	Intel	?	?	[28][29]
1978	EA8316F	16 kb	ROM	NMOS	Electronic Arrays	?	436 mm²	[22][30]
1978	µCOM-43 (CMOS)	16 kb	PROM	CMOS	NEC	?	?	[27]
1978	2732	32 kb	EPROM	NMOS ( HMOS )	Intel	?	?	[24][31]
1978	2364	64 kb	ROM	NMOS	Intel	?	?	[32]
1980	?	16 kb	EEPROM	NMOS	Motorola	4,000 nm	?	[24][33]
1981	2764	64 kb	EPROM	NMOS ( HMOS II )	Intel	3,500 nm	?	[24][33][34]
1982	?	32 kb	EEPROM	MOS	Motorola	?	?	[33]
1982	27128	128 kb	EPROM	NMOS (HMOS II)	Intel	?	?	[24][33][35]
1983	?	64 kb	EPROM	CMOS	Signetics	3,000 nm	?	[33]
1983	27256	256 kb	EPROM	NMOS (HMOS)	Intel	?	?	[24][36]
1983	?	256 kb	EPROM	CMOS	Fujitsu	?	?	[37]
January 1984	MBM 2764	64 kb	EEPROM	NMOS	Fujitsu	?	528 mm²	[38]
1984	?	512 kb	EPROM	NMOS	AMD	1,700 nm	?	[33]
1984	27512	512 kb	EPROM	NMOS (HMOS)	Intel	?	?	[24][39]
1984	?	1 Mb	EPROM	CMOS	NEC	1,200 nm	?	[33]
1987	?	4 Mb	EPROM	CMOS	Toshiba	800 nm	?	[33]
1990	?	16 Mb	EPROM	CMOS	NEC	600 nm	?	[33]
1993	?	8 Mb	MROM	CMOS	Hyundai	?	?	[40]
1995	?	1 Mb	EEPROM	CMOS	Hitachi	?	?	[41]
1995	?	16 Mb	MROM	CMOS	AKM, Hitachi	?	?	[41]

See also

• Flash memory
• Random access memory
• Read-mostly memory (RMM)
• Write-only memory

Notes

1. ^ Other terms are used as well, e.g., "Initial Program Load" (IPL).

References

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