Electronic design automation

Electronic design automation (EDA), also referred to as electronic computer-aided design (ECAD),

The earliest electronic design automation is attributed to IBM with the documentation of its 700 series computers in the 1950s.^[2]

Prior to the development of EDA, integrated circuits were designed by hand and manually laid out.^[3] Some advanced shops used geometric software to generate tapes for a Gerber photoplotter, responsible for generating a monochromatic exposure image, but even those copied digital recordings of mechanically drawn components. The process was fundamentally graphic, with the translation from electronics to graphics done manually; the best-known company from this era was Calma, whose GDSII format is still in use today. By the mid-1970s, developers started to automate circuit design in addition to drafting and the first placement and routing tools were developed; as this occurred, the proceedings of the Design Automation Conference catalogued the large majority of the developments of the time.^[3]

The next era began following the publication of "Introduction to VLSI Systems" by Carver Mead and Lynn Conway in 1980,^[4] and is considered the standard textbook for chip design.^[5] The result was an increase in the complexity of the chips that could be designed, with improved access to design verification tools that used logic simulation. The chips were easier to lay out and more likely to function correctly, since their designs could be simulated more thoroughly prior to construction. Although the languages and tools have evolved, this general approach of specifying the desired behavior in a textual programming language and letting the tools derive the detailed physical design remains the basis of digital IC design today.

The earliest EDA tools were produced academically. One of the most famous was the "Berkeley VLSI Tools Tarball", a set of

1981 marked the beginning of EDA as an industry. For many years, the larger electronic companies, such as

The first trade show for EDA was held at the Design Automation Conference in 1984 and in 1986, Verilog, another popular high-level design language, was first introduced as a hardware description language by Gateway Design Automation. Simulators quickly followed these introductions, permitting direct simulation of chip designs and executable specifications. Within several years, back-ends were developed to perform logic synthesis.

Current digital flows are extremely modular, with front ends producing standardized design descriptions that compile into invocations of units similar to cells without regard to their individual technology. Cells implement logic or other electronic functions via the utilisation of a particular integrated circuit technology. Fabricators generally provide libraries of components for their production processes, with simulation models that fit standard simulation tools.

Most analog circuits are still designed in a manual fashion, requiring specialist knowledge that is unique to analog design (such as matching concepts).^[9] Hence, analog EDA tools are far less modular, since many more functions are required, they interact more strongly and the components are, in general, less ideal.

EDA for electronics has rapidly increased in importance with the continuous scaling of

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Design flow primarily remains characterised via several primary components; these include:

• High-level synthesis (additionally known as behavioral synthesis or algorithmic synthesis) – The high-level design description (e.g. in C/C++) is converted into RTL or the register transfer level, responsible for representing circuitry via the utilisation of interactions between registers.
• Logic synthesis – The translation of RTL design description (e.g. written in Verilog or VHDL) into a discrete netlist or representation of logic gates.
• Schematic capture – For standard cell digital, analog, RF-like Capture CIS in Orcad by Cadence and ISIS in Proteus.^{[clarification needed]}
• Layout – usually schematic-driven layout
  , like Layout in Orcad by Cadence, ARES in Proteus

• Transistor simulation – low-level transistor-simulation of a schematic/layout's behavior, accurate at device-level.
• Logic simulation – digital-simulation of an RTL or gate-netlist's digital (Boolean 0/1) behavior, accurate at Boolean-level.
• Behavioral simulation – high-level simulation of a design's architectural operation, accurate at cycle-level or interface-level.
• Hardware emulation – Use of special purpose hardware to emulate the logic of a proposed design. Can sometimes be plugged into a system in place of a yet-to-be-built chip; this is called in-circuit emulation.
• Technology CAD simulate and analyze the underlying process technology. Electrical properties of devices are derived directly from device physics

• Functional verification: ensures logic design matches specifications and executes tasks correctly. Includes dynamic functional verification via simulation, emulation, and prototypes.^[11]
• RTL Linting for adherence to coding rules such as syntax, semantics, and style.^[12]
• clock domains
  in the design.
• Formal verification, also model checking: attempts to prove, by mathematical methods, that the system has certain desired properties, and that some undesired effects (such as deadlock) cannot occur.
• Equivalence checking: algorithmic comparison between a chip's RTL-description and synthesized gate-netlist, to ensure functional equivalence at the logical level.
• Static timing analysis: analysis of the timing of a circuit in an input-independent manner, hence finding a worst case over all possible inputs.
• Layout extraction
  : starting with a proposed layout, compute the (approximate) electrical characteristics of every wire and device. Often used in conjunction with static timing analysis above to estimate the performance of the completed chip.
• layout extraction
  above.
• Physical verification, PV: checking if a design is physically manufacturable, and that the resulting chips will not have any function-preventing physical defects, and will meet original specifications.

• Mask data preparation or MDP - The generation of actual lithography photomasks, utilised to physically manufacture the chip.
  • Chip finishing which includes custom designations and structures to improve
    manufacturability of the layout. Examples of the latter are a seal ring and filler structures.^[13]
  • Producing a reticle layout with test patterns and alignment marks.
  • Layout-to-mask preparation that enhances layout data with graphics operations, such as
    interference
    effects occurring later when chip is manufactured using this mask.
  • Mask generation
    – The generation of flat mask image from hierarchical design.
  • Automatic test pattern generation or ATPG – The generation of pattern data systematically to exercise as many logic-gates and other components as possible.
  • Built-in self-test or BIST – The installation of self-contained test-controllers to automatically test a logic or memory structure in the design

• failure in time
  (FIT) rates and diagnostic coverage metrics for designs in order to meet the compliance requirements for the desired safety integrity levels.
• Functional safety synthesis, add reliability enhancements to structured elements (modules, RAMs, ROMs, register files, FIFOs) to improve fault detection / fault tolerance. This includes (not limited to) addition of error detection and / or correction codes (Hamming), redundant logic for fault detection and fault tolerance (duplicate / triplicate) and protocol checks (interface parity, address alignment, beat count)
• Functional safety verification, running of a fault campaign, including insertion of faults into the design and verification that the safety mechanism reacts in an appropriate manner for the faults that are deemed covered.

Market capitalization and company name as of March 2023:

• $57.87 billion^[14] – Synopsys
• $56.68 billion^[15] – Cadence Design Systems
• $24.98 billion^[16] – Ansys
• AU$4.88 billion^[17] – Altium
• ¥77.25 billion^[18] – Zuken

Market capitalization and company name as of December 2011^[update]:^[19]

• $2.33 billion – Mentor Graphics; Siemens acquired Mentor in 2017 and renamed as Siemens EDA in 2021^[20][21]
• $507 million – Magma Design Automation; Synopsys acquired Magma in February 2012^[22][23]
• NT$6.44 billion –
  SpringSoft
  ; Synopsys acquired SpringSoft in August 2012

Many EDA companies acquire small companies with software or other technology that can be adapted to their core business.

• Design Automation Conference
• International Conference on Computer-Aided Design
• Design Automation and Test in Europe
• Asia and South Pacific Design Automation Conference
• Symposia on VLSI Technology and Circuits

Wikimedia Commons has media related to Electronic design automation.

• Computer-aided design (CAD)
• Circuit design
• EDA database
• Foundations and Trends in Electronic Design Automation
• Signoff (electronic design automation)
• Comparison of EDA software
• Platform-based design
• Silicon compiler