Hybrid Memory Cube
Hybrid Memory Cube (HMC) is a high-performance computer random-access memory (RAM) interface for through-silicon via (TSV)-based stacked DRAM memory. HMC competes with the incompatible rival interface High Bandwidth Memory (HBM).
Overview
Hybrid Memory Cube was co-developed by
HMC combines
HMC uses standard DRAM cells but it has more data banks than classic
HMC technology won the Best New Technology award from The Linley Group (publisher of Microprocessor Report magazine) in 2011.[9][10]
The first public specification, HMC 1.0, was published in April 2013.
The typical raw
As reported at the HotChips 23 conference in 2011, the first generation of HMC demonstration cubes with four 50 nm DRAM memory dies and one 90 nm logic die with total capacity of 512 MB and size 27×27 mm had power consumption of 11 W and was powered with 1.2 V.[7]
Engineering samples of second generation HMC memory chips were shipped in September 2013 by Micron.[3] Samples of 2 GB HMC (stack of 4 memory dies, each of 4 Gbit) are packed in a 31×31 mm package and have 4 HMC links. Other samples from 2013 have only two HMC links and a smaller package: 16×19.5 mm.[16]
The second version of the HMC specification was published on 18 November 2014 by HMCC.
The first processor to use HMCs was the Fujitsu SPARC64 XIfx,[19] which is used in the Fujitsu PRIMEHPC FX100 supercomputer introduced in 2015.
JEDEC's Wide I/O and Wide I/O 2 are seen as the mobile computing counterparts to the desktop/server-oriented HMC in that both involve 3D die stacks.[20]
In August 2018, Micron announced a move away from HMC to pursue competing high-performance memory technologies such as
See also
References
- ISBN 9783319186757. Archived from the original(PDF) on 23 October 2021. Retrieved 19 July 2019.
- ^ a b Micron Reinvents DRAM Memory, Linley Group, Jag Bolaria, 12 September 2011
- ^ a b Mearian, Lucas (25 September 2013). "Micron ships Hybrid Memory Cube that boosts DRAM 15X". computerworld.com. Computerworld. Retrieved 4 November 2014.
- ^ Microsoft backs Hybrid Memory Cube tech // by Gareth Halfacree, bit-tech, 9 May 2012
- ^ "About Us". Hybrid Memory Cube Consortium. Archived from the original on 10 October 2011. Retrieved 10 October 2011.
- ^ "FAQs". www.micron.com. Retrieved 5 December 2018.
- ^ a b c Hybrid Memory Cube (HMC), J. Thomas Pawlowski (Micron) // HotChips 23
- ^ Memory for Exascale and ... Micron's new memory component is called HMC: Hybrid Memory Cube Archived 17 April 2012 at the Wayback Machine by Dave Resnick (Sandia National Laboratories) // 2011 Workshop on Architectures I: Exascale and Beyond, 8 July 2011
- ^ Micron's Hybrid Memory Cubes win tech award // by Gareth Halfacree, bit-tech, 27 January 2012
- ^ Best Processor Technology of 2011 // The Linley Group, Tom Halfhill, 23 Jan 2012
- ^ Hybrid Memory Cube receives its finished spec, promises up to 320 GB per second By Jon Fingas // Engadget, 3 April 2013
- ^ HMC 1.0 Specification, Chapter "1 HMC Architecture"
- ^ HMC 1.0 Specification, Chapter "5 Chaining"
- ^ HMC 1.0 Specification, Chapter "19 Packages for HMC-15G-SR Devices"
- ^ "Hybrid Memory Cube Specification 1.0" (PDF). HMC Consortium. 1 January 2013. Archived from the original (PDF) on 13 May 2013. Retrieved 10 August 2016.
- ^ Hruska, Joel (25 September 2013). "Hybrid Memory Cube 160GB/sec RAM starts shipping: Is this the technology that finally kills DDR RAM?". Extremetech. Extreme Tech. Retrieved 27 September 2013.
- ^ Hybrid Memory Cube Consortium Advances Hybrid Memory Cube Performance and Industry Adoption With Release of New Specification Archived 1 August 2016 at the Wayback Machine, 18 November 2014
- ^ "Hybrid Memory Cube Specification 2.1" (PDF). HMC Consortium. 5 November 2015. Archived from the original (PDF) on 9 January 2016. Retrieved 10 August 2016.
- ^ Halfhill, Tom R. (22 September 2014). "Sparc64 XIfx Uses Memory Cubes". Microprocessor Report.
- ^ Goering, Richard (6 August 2013). "Wide I/O 2, Hybrid Memory Cube (HMC) – Memory Models Advance 3D-IC Standards". cadence.com. Cadence Design Systems. Retrieved 8 December 2014.
- ^ "Micron Announces Shift in High-Performance Memory Roadmap Strategy".
External links
- Official website of the Hybrid Memory Cube Consortium
- HMC 1.0 Specification
- HMC 2.0 Specification download form Archived 17 June 2019 at the Wayback Machine
- Revolutionary Advancements in Memory Performance on YouTube
- Hybrid Memory Cube (HMC) Archived 23 April 2014 at the Wayback Machine, J. Thomas Pawlowski (Micron) // HotChips 23, 2011
- Stacking Stairs Against the Memory Wall Archived 1 August 2016 at the Wayback Machine by Nicole Hemsoth // HPC Wire, 2 April 2013