Micro-operation
In
Usually, micro-operations perform basic operations on data stored in one or more
Optimizations
Various forms of μops have long been the basis for traditional
This buffering means that the fetch and decode stages can be more detached from the execution units than is feasible in a more traditional microcoded (or hard-wired) design. As this allows a degree of freedom regarding execution order, it makes some extraction of instruction-level parallelism out of a normal single-threaded program possible (provided that dependencies are checked, etc.). It opens up for more analysis and therefore also for reordering of code sequences in order to dynamically optimize mapping and scheduling of μops onto machine resources (such as ALUs, load/store units, etc.). As this happens on the μop-level, sub-operations of different machine (macro) instructions may often intermix in a particular μop-sequence, forming partially reordered machine instructions as a direct consequence of the out-of-order dispatching of microinstructions from several macro instructions. However, this is not the same as the micro-op fusion, which aims at the fact that a more complex microinstruction may replace a few simpler microinstructions in certain cases, typically in order to minimize state changes and usage of the queue and re-order buffer space, therefore reducing power consumption. Micro-op fusion is used in some modern CPU designs.[3]: 89–91, 105–106 [4]: 6–7, 9–15
Execution optimization has gone even further; processors not only translate many machine instructions into a series of μops, but also do the opposite when appropriate; they combine certain machine instruction sequences (such as a compare followed by a conditional jump) into a more complex μop which fits the execution model better and thus can be executed faster or with less machine resources involved. This is also known as macro-op fusion.[3]: 106–107 [4]: 12–13
Another way to try to improve performance is to cache the decoded micro-operations in a
References
- ^ a b "Computer Organization and Architecture, Chapter 15. Control Unit Operation" (PDF). umcs.maine.edu. 2010-03-16. Retrieved 2014-12-29.
- Ferranti Limited, Digital Systems Department. October 1968 [September 1968]. List DSD 68/6. Archived(PDF) from the original on 2020-05-19. Retrieved 2020-05-19.
- ^ a b c Agner Fog (2014-02-19). "The microarchitecture of Intel, AMD and VIA CPUs: An optimization guide for assembly programmers and compiler makers" (PDF). agner.org. Retrieved 2014-03-21.
- ^ a b c Michael E. Thomadakis (2011-03-17). "The Architecture of the Nehalem Processor and Nehalem-EP SMP Platforms" (PDF). Texas A&M University. Archived from the original (PDF) on 2014-08-11. Retrieved 2014-03-21.
- ^ "Intel Pentium 4 1.4GHz & 1.5GHz". AnandTech. 2000-11-20. Retrieved 2013-10-06.
- S2CID 10934861. Retrieved 2014-03-21.