MIPS-X
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Bits | 32-bit |
---|---|
Introduced | 1987 |
Design | RISC |
Predecessor | Stanford MIPS |
MIPS-X is a
Integrated Information Technology (IIT) for use in digital video
applications.
MIPS-X, while designed by the same team and architecturally very similar, is instruction-set incompatible with the mainline MIPS architecture R-series processors. The MIPS-X processor introduced the concept of a delayed branch, which includes two delay slots.[1] An MIPS-X processor also includes a Processor Status Word (PSW) register. The PSW register contains some flags that enable interruptions, overflow exceptions and other status information.[2] The MIPS-X processor is obscure enough that, as of November 20, 2005, support for it is provided only by specialist developers (such as Green Hills Software), and is notably missing from the GNU Compiler Collection (GCC).
MIPS-X has become important among
hackers, since many DVD players (especially low-end devices) use chips based on the IIT design (and produced by ESS Technology), as their central processor. Devices such as the ESS VideoDrive system on a chip (SoC) also include a digital signal processor
(DSP) (coprocessor) for decoding MPEG audio and video streams.
References
- ^ "MIPS-X Instruction Set and Programmer's Manual" (PDF). p. 18. Retrieved 2023-12-03.
- ^ "MIPS-X Instruction Set and Programmer's Manual" (PDF). pp. 13–14. Retrieved 2023-12-07.
External links
- The original MIPS-X paper from Stanford